Lines Matching +full:0 +full:x35000000
40 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
46 ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
51 if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890) in ppc440spe_revA()
54 return 0; in ppc440spe_revA()
62 if (dev->devfn != 0 || dev->bus->self != NULL) in fixup_ppc4xx_pci_bridge()
83 r->start = r->end = 0; in fixup_ppc4xx_pci_bridge()
84 r->flags = 0; in fixup_ppc4xx_pci_bridge()
101 res->start = 0; in ppc4xx_parse_dma_ranges()
102 size = 0x80000000; in ppc4xx_parse_dma_ranges()
115 if (cpu_addr == OF_BAD_ADDR || size == 0) in ppc4xx_parse_dma_ranges()
119 if ((pci_space & 0x03000000) != 0x02000000) in ppc4xx_parse_dma_ranges()
122 /* We currently only support memory at 0, and pci_addr in ppc4xx_parse_dma_ranges()
125 if (cpu_addr != 0 || pci_addr > 0xffffffff) { in ppc4xx_parse_dma_ranges()
127 " 0x%016llx...0x%016llx -> 0x%016llx\n", in ppc4xx_parse_dma_ranges()
134 if (!(pci_space & 0x40000000)) in ppc4xx_parse_dma_ranges()
142 (pci_addr + size) > 0x100000000ull) in ppc4xx_parse_dma_ranges()
143 res->end = 0xffffffff; in ppc4xx_parse_dma_ranges()
166 if ((size & (size - 1)) != 0 || in ppc4xx_parse_dma_ranges()
167 (res->start & (size - 1)) != 0) { in ppc4xx_parse_dma_ranges()
175 if (res->end > 0xffffffff && in ppc4xx_parse_dma_ranges()
188 printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n", in ppc4xx_parse_dma_ranges()
190 printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n", in ppc4xx_parse_dma_ranges()
192 printk(KERN_INFO "DMA window size 0x%016llx\n", in ppc4xx_parse_dma_ranges()
194 return 0; in ppc4xx_parse_dma_ranges()
214 * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx. in ppc4xx_setup_one_pci_PMM()
222 plb_addr &= 0xffffffffull; in ppc4xx_setup_one_pci_PMM()
228 if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) || in ppc4xx_setup_one_pci_PMM()
229 size < 0x1000 || (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pci_PMM()
233 ma = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_setup_one_pci_PMM()
240 writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
241 writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
242 writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
243 writel(ma, reg + PCIL0_PMM0MA + (0x10 * index)); in ppc4xx_setup_one_pci_PMM()
245 return 0; in ppc4xx_setup_one_pci_PMM()
251 int i, j, found_isa_hole = 0; in ppc4xx_configure_pci_PMMs()
254 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pci_PMMs()
272 j) == 0) { in ppc4xx_configure_pci_PMMs()
275 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pci_PMMs()
285 if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pci_PMMs()
286 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pci_PMMs()
299 sa = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_configure_pci_PTMs()
300 sa |= 0x1; in ppc4xx_configure_pci_PTMs()
302 /* RAM is always at 0 local for now */ in ppc4xx_configure_pci_PTMs()
303 writel(0, reg + PCIL0_PTM1LA); in ppc4xx_configure_pci_PTMs()
307 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
309 early_write_config_dword(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
310 PCI_BASE_ADDRESS_2, 0x00000000); in ppc4xx_configure_pci_PTMs()
311 early_write_config_word(hose, hose->first_busno, 0, in ppc4xx_configure_pci_PTMs()
312 PCI_COMMAND, 0x0006); in ppc4xx_configure_pci_PTMs()
324 int primary = 0; in ppc4xx_probe_pci_bridge()
333 if (of_address_to_resource(np, 0, &rsrc_cfg)) { in ppc4xx_probe_pci_bridge()
364 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pci_bridge()
365 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pci_bridge()
368 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0); in ppc4xx_probe_pci_bridge()
371 writel(0, reg + PCIL0_PMM0MA); in ppc4xx_probe_pci_bridge()
372 writel(0, reg + PCIL0_PMM1MA); in ppc4xx_probe_pci_bridge()
373 writel(0, reg + PCIL0_PMM2MA); in ppc4xx_probe_pci_bridge()
374 writel(0, reg + PCIL0_PTM1MS); in ppc4xx_probe_pci_bridge()
375 writel(0, reg + PCIL0_PTM2MS); in ppc4xx_probe_pci_bridge()
381 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) in ppc4xx_probe_pci_bridge()
415 if (!is_power_of_2(size) || size < 0x1000 || in ppc4xx_setup_one_pcix_POM()
416 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pcix_POM()
427 sa = (0xffffffffu << ilog2(size)) | 0x1; in ppc4xx_setup_one_pcix_POM()
430 if (index == 0) { in ppc4xx_setup_one_pcix_POM()
444 return 0; in ppc4xx_setup_one_pcix_POM()
450 int i, j, found_isa_hole = 0; in ppc4xx_configure_pcix_POMs()
453 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pcix_POMs()
471 j) == 0) { in ppc4xx_configure_pcix_POMs()
474 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pcix_POMs()
484 if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0, in ppc4xx_configure_pcix_POMs()
485 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pcix_POMs()
499 /* RAM is always at 0 */ in ppc4xx_configure_pcix_PIMs()
500 writel(0x00000000, reg + PCIX0_PIM0LAH); in ppc4xx_configure_pcix_PIMs()
501 writel(0x00000000, reg + PCIX0_PIM0LAL); in ppc4xx_configure_pcix_PIMs()
504 sa = (0xffffffffu << ilog2(size)) | 1; in ppc4xx_configure_pcix_PIMs()
505 sa |= 0x1; in ppc4xx_configure_pcix_PIMs()
507 sa |= 0x2; in ppc4xx_configure_pcix_PIMs()
509 sa |= 0x4; in ppc4xx_configure_pcix_PIMs()
512 writel(0xffffffff, reg + PCIX0_PIM0SAH); in ppc4xx_configure_pcix_PIMs()
515 writel(0x00000000, reg + PCIX0_BAR0H); in ppc4xx_configure_pcix_PIMs()
517 writew(0x0006, reg + PCIX0_COMMAND); in ppc4xx_configure_pcix_PIMs()
531 if (of_address_to_resource(np, 0, &rsrc_cfg)) { in ppc4xx_probe_pcix_bridge()
567 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_probe_pcix_bridge()
568 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_probe_pcix_bridge()
571 setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, in ppc4xx_probe_pcix_bridge()
575 writel(0, reg + PCIX0_POM0SA); in ppc4xx_probe_pcix_bridge()
576 writel(0, reg + PCIX0_POM1SA); in ppc4xx_probe_pcix_bridge()
577 writel(0, reg + PCIX0_POM2SA); in ppc4xx_probe_pcix_bridge()
578 writel(0, reg + PCIX0_PIM0SA); in ppc4xx_probe_pcix_bridge()
579 writel(0, reg + PCIX0_PIM1SA); in ppc4xx_probe_pcix_bridge()
580 writel(0, reg + PCIX0_PIM2SA); in ppc4xx_probe_pcix_bridge()
582 writel(0, reg + PCIX0_PIM0SAH); in ppc4xx_probe_pcix_bridge()
583 writel(0, reg + PCIX0_PIM2SAH); in ppc4xx_probe_pcix_bridge()
590 if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0) in ppc4xx_probe_pcix_bridge()
626 #define MAX_PCIE_BUS_MAPPED 0x40
670 return 0; in ppc4xx_pciex_wait_on_sdr()
680 if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) { in ppc4xx_pciex_port_reset_sdr()
685 return 0; in ppc4xx_pciex_port_reset_sdr()
707 0x1000, 0x1000, 2000)) in ppc4xx_pciex_check_link_sdr()
725 int err = 0; in ppc440spe_pciex_check_reset()
728 if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) { in ppc440spe_pciex_check_reset()
736 mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
737 mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
738 mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000); in ppc440spe_pciex_check_reset()
746 if (!(valPE0 & 0x01000000) || in ppc440spe_pciex_check_reset()
747 !(valPE1 & 0x01000000) || in ppc440spe_pciex_check_reset()
748 !(valPE2 & 0x01000000)) { in ppc440spe_pciex_check_reset()
754 if (!(valPE0 & 0x00010000) || in ppc440spe_pciex_check_reset()
755 !(valPE1 & 0x00010000) || in ppc440spe_pciex_check_reset()
756 !(valPE2 & 0x00010000)) { in ppc440spe_pciex_check_reset()
762 if ((valPE0 & 0x00001000) || in ppc440spe_pciex_check_reset()
763 (valPE1 & 0x00001000) || in ppc440spe_pciex_check_reset()
764 (valPE2 & 0x00001000)) { in ppc440spe_pciex_check_reset()
770 if ((valPE0 & 0x10000000) || in ppc440spe_pciex_check_reset()
771 (valPE1 & 0x10000000) || in ppc440spe_pciex_check_reset()
772 (valPE2 & 0x10000000)) { in ppc440spe_pciex_check_reset()
778 if ((valPE0 & 0x00100000) || in ppc440spe_pciex_check_reset()
779 (valPE1 & 0x00100000) || in ppc440spe_pciex_check_reset()
780 (valPE2 & 0x00100000)) { in ppc440spe_pciex_check_reset()
786 if ((valPE0 & 0x00000100) || in ppc440spe_pciex_check_reset()
787 (valPE1 & 0x00000100) || in ppc440spe_pciex_check_reset()
788 (valPE2 & 0x00000100)) { in ppc440spe_pciex_check_reset()
802 dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28); in ppc440spe_pciex_core_init()
808 if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) { in ppc440spe_pciex_core_init()
810 "failed (0x%08x)\n", in ppc440spe_pciex_core_init()
816 dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0); in ppc440spe_pciex_core_init()
820 if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) { in ppc440spe_pciex_core_init()
845 if (port->index == 0) in ppc440spe_pciex_init_port_hw()
851 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222); in ppc440spe_pciex_init_port_hw()
853 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000); in ppc440spe_pciex_init_port_hw()
854 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
855 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
856 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
857 mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000); in ppc440spe_pciex_init_port_hw()
858 if (port->index == 0) { in ppc440spe_pciex_init_port_hw()
860 0x35000000); in ppc440spe_pciex_init_port_hw()
862 0x35000000); in ppc440spe_pciex_init_port_hw()
864 0x35000000); in ppc440spe_pciex_init_port_hw()
866 0x35000000); in ppc440spe_pciex_init_port_hw()
891 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800); in ppc440speA_pciex_init_utl()
896 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc440speA_pciex_init_utl()
897 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc440speA_pciex_init_utl()
898 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
899 out_be32(port->utl_base + PEUTL_PBBSZ, 0x53000000); in ppc440speA_pciex_init_utl()
900 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x08000000); in ppc440speA_pciex_init_utl()
901 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x10000000); in ppc440speA_pciex_init_utl()
902 out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000); in ppc440speA_pciex_init_utl()
903 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc440speA_pciex_init_utl()
905 return 0; in ppc440speA_pciex_init_utl()
911 out_be32(port->utl_base + PEUTL_PBCTL, 0x08000000); in ppc440speB_pciex_init_utl()
913 return 0; in ppc440speB_pciex_init_utl()
950 if (port->index == 0) { in ppc460ex_pciex_init_port_hw()
952 utlset1 = 0x20000000; in ppc460ex_pciex_init_port_hw()
955 utlset1 = 0x20101101; in ppc460ex_pciex_init_port_hw()
960 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000); in ppc460ex_pciex_init_port_hw()
963 case 0: in ppc460ex_pciex_init_port_hw()
964 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
965 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
966 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
968 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
972 mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
973 mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
974 mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
975 mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230); in ppc460ex_pciex_init_port_hw()
976 mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
977 mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
978 mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
979 mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130); in ppc460ex_pciex_init_port_hw()
980 mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
981 mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
982 mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
983 mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006); in ppc460ex_pciex_init_port_hw()
985 mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000); in ppc460ex_pciex_init_port_hw()
996 case 0: in ppc460ex_pciex_init_port_hw()
997 while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1)) in ppc460ex_pciex_init_port_hw()
1001 while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1)) in ppc460ex_pciex_init_port_hw()
1018 dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0); in ppc460ex_pciex_init_utl()
1023 out_be32(port->utl_base + PEUTL_PBCTL, 0x0800000c); in ppc460ex_pciex_init_utl()
1024 out_be32(port->utl_base + PEUTL_OUTTR, 0x08000000); in ppc460ex_pciex_init_utl()
1025 out_be32(port->utl_base + PEUTL_INTR, 0x02000000); in ppc460ex_pciex_init_utl()
1026 out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1027 out_be32(port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460ex_pciex_init_utl()
1028 out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000); in ppc460ex_pciex_init_utl()
1029 out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000); in ppc460ex_pciex_init_utl()
1030 out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000); in ppc460ex_pciex_init_utl()
1031 out_be32(port->utl_base + PEUTL_PCTL, 0x80800066); in ppc460ex_pciex_init_utl()
1033 return 0; in ppc460ex_pciex_init_utl()
1063 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0); in apm821xx_pciex_init_port_hw()
1074 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000); in apm821xx_pciex_init_port_hw()
1075 mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000); in apm821xx_pciex_init_port_hw()
1077 mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230); in apm821xx_pciex_init_port_hw()
1078 mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130); in apm821xx_pciex_init_port_hw()
1079 mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006); in apm821xx_pciex_init_port_hw()
1081 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000); in apm821xx_pciex_init_port_hw()
1083 mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000); in apm821xx_pciex_init_port_hw()
1091 if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) { in apm821xx_pciex_init_port_hw()
1101 return 0; in apm821xx_pciex_init_port_hw()
1116 mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1117 mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1118 mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1119 mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1120 mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1121 mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1122 mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1123 mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1125 mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1126 mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1127 mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1128 mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1130 mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1131 mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1132 mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1133 mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211); in ppc460sx_pciex_core_init()
1136 mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1137 mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1138 mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1139 mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1140 mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1141 mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1142 mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1143 mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1145 mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1146 mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1147 mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1148 mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1150 mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1151 mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1152 mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1153 mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987); in ppc460sx_pciex_core_init()
1156 mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222); in ppc460sx_pciex_core_init()
1157 mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1158 mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000); in ppc460sx_pciex_core_init()
1161 mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF); in ppc460sx_pciex_core_init()
1162 mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1163 mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000); in ppc460sx_pciex_core_init()
1166 mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1167 mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130); in ppc460sx_pciex_core_init()
1172 dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0); in ppc460sx_pciex_core_init()
1188 if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) == in ppc460sx_pciex_core_init()
1189 0x00000001)) { in ppc460sx_pciex_core_init()
1204 0x01000000, 0); in ppc460sx_pciex_init_port_hw()
1207 0, 0x01000000); in ppc460sx_pciex_init_port_hw()
1221 out_be32 (port->utl_base + PEUTL_PBBSZ, 0x00000000); in ppc460sx_pciex_init_utl()
1223 out_be32(port->utl_base + PEUTL_PCTL, 0x80800000); in ppc460sx_pciex_init_utl()
1224 return 0; in ppc460sx_pciex_init_utl()
1232 port->link = 0; in ppc460sx_pciex_check_link()
1234 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc460sx_pciex_check_link()
1241 while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA) in ppc460sx_pciex_check_link()
1270 u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT); in ppc_476fpe_pciex_check_link()
1271 void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000, in ppc_476fpe_pciex_check_link()
1272 0x1000); in ppc_476fpe_pciex_check_link()
1313 return 0; in ppc4xx_pciex_check_core_init()
1340 if (count > 0) { in ppc4xx_pciex_check_core_init()
1346 return 0; in ppc4xx_pciex_check_core_init()
1363 dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001); in ppc4xx_pciex_port_init_mapping()
1372 dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001); in ppc4xx_pciex_port_init_mapping()
1375 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1376 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1377 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0); in ppc4xx_pciex_port_init_mapping()
1378 dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0); in ppc4xx_pciex_port_init_mapping()
1383 int rc = 0; in ppc4xx_pciex_port_init()
1388 if (rc != 0) in ppc4xx_pciex_port_init()
1403 port->utl_base = ioremap(port->utl_regs.start, 0x100); in ppc4xx_pciex_port_init()
1423 port->link = 0; in ppc4xx_pciex_port_init()
1430 port->link = 0; in ppc4xx_pciex_port_init()
1433 dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20); in ppc4xx_pciex_port_init()
1438 return 0; in ppc4xx_pciex_port_init()
1462 if (bus->number == port->hose->first_busno && devfn != 0) in ppc4xx_pciex_validate_bdf()
1467 PCI_SLOT(devfn) != 0) in ppc4xx_pciex_validate_bdf()
1474 return 0; in ppc4xx_pciex_validate_bdf()
1505 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_read_config()
1519 out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000); in ppc4xx_pciex_read_config()
1533 pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_read_config()
1534 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", in ppc4xx_pciex_read_config()
1539 if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) { in ppc4xx_pciex_read_config()
1541 if (len != 4 || offset != 0) in ppc4xx_pciex_read_config()
1543 *val = 0xffff0001; in ppc4xx_pciex_read_config()
1560 if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0) in ppc4xx_pciex_write_config()
1573 pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x" in ppc4xx_pciex_write_config()
1574 " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n", in ppc4xx_pciex_write_config()
1613 (index < 2 && size < 0x100000) || in ppc4xx_setup_one_pciex_POM()
1614 (index == 2 && size < 0x100) || in ppc4xx_setup_one_pciex_POM()
1615 (plb_addr & (size - 1)) != 0) { in ppc4xx_setup_one_pciex_POM()
1625 sa = (0xffffffffu << ilog2(size)) | 0x1; in ppc4xx_setup_one_pciex_POM()
1629 case 0: in ppc4xx_setup_one_pciex_POM()
1634 dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1657 dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1666 dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff); in ppc4xx_setup_one_pciex_POM()
1674 return 0; in ppc4xx_setup_one_pciex_POM()
1681 int i, j, found_isa_hole = 0; in ppc4xx_configure_pciex_POMs()
1684 for (i = j = 0; i < 3; i++) { in ppc4xx_configure_pciex_POMs()
1703 j) == 0) { in ppc4xx_configure_pciex_POMs()
1706 /* If the resource PCI address is 0 then we have our in ppc4xx_configure_pciex_POMs()
1717 hose->isa_mem_phys, 0, in ppc4xx_configure_pciex_POMs()
1718 hose->isa_mem_size, 0, j) == 0) in ppc4xx_configure_pciex_POMs()
1722 /* Configure IO, always 64K starting at 0. We hard wire it to 64K ! in ppc4xx_configure_pciex_POMs()
1727 hose->io_base_phys, 0, in ppc4xx_configure_pciex_POMs()
1728 0x10000, IORESOURCE_IO, 2); in ppc4xx_configure_pciex_POMs()
1740 resource_size_t ep_addr = 0; in ppc4xx_configure_pciex_PIMs()
1744 * 0 (SDRAM). This should probably be configurable via a dts in ppc4xx_configure_pciex_PIMs()
1749 sa = (0xffffffffffffffffull << ilog2(ep_size)); in ppc4xx_configure_pciex_PIMs()
1757 out_le32(mbase + PECFG_BAR1MPA, 0); in ppc4xx_configure_pciex_PIMs()
1758 out_le32(mbase + PECFG_BAR2HMPA, 0); in ppc4xx_configure_pciex_PIMs()
1759 out_le32(mbase + PECFG_BAR2LMPA, 0); in ppc4xx_configure_pciex_PIMs()
1768 sa = (0xffffffffffffffffull << ilog2(size)); in ppc4xx_configure_pciex_PIMs()
1785 out_le32(mbase + PECFG_PIM0LAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1786 out_le32(mbase + PECFG_PIM0LAH, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1787 out_le32(mbase + PECFG_PIM1LAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1788 out_le32(mbase + PECFG_PIM1LAH, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1789 out_le32(mbase + PECFG_PIM01SAH, 0xffff0000); in ppc4xx_configure_pciex_PIMs()
1790 out_le32(mbase + PECFG_PIM01SAL, 0x00000000); in ppc4xx_configure_pciex_PIMs()
1797 out_le32(mbase + PECFG_PIMEN, 0x1); in ppc4xx_configure_pciex_PIMs()
1832 hose->first_busno = bus_range ? bus_range[0] : 0x0; in ppc4xx_pciex_port_setup_hose()
1833 hose->last_busno = bus_range ? bus_range[1] : 0xff; in ppc4xx_pciex_port_setup_hose()
1851 (hose->first_busno + 1) * 0x100000, in ppc4xx_pciex_port_setup_hose()
1852 busses * 0x100000); in ppc4xx_pciex_port_setup_hose()
1864 mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000); in ppc4xx_pciex_port_setup_hose()
1874 pr_debug(" config space mapped at: root @0x%p, other @0x%p\n", in ppc4xx_pciex_port_setup_hose()
1894 out_le32(mbase + PECFG_PIMEN, 0); in ppc4xx_pciex_port_setup_hose()
1900 if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0) in ppc4xx_pciex_port_setup_hose()
1922 val = 0xaaa0 + port->index; in ppc4xx_pciex_port_setup_hose()
1924 val = 0xeee0 + port->index; in ppc4xx_pciex_port_setup_hose()
1926 out_le16(mbase + 0x200, val); in ppc4xx_pciex_port_setup_hose()
1933 val = 0xbed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1935 val = 0xfed0 + port->index; in ppc4xx_pciex_port_setup_hose()
1937 out_le16(mbase + 0x202, val); in ppc4xx_pciex_port_setup_hose()
1941 out_le16(mbase + 0x204, 0x7); in ppc4xx_pciex_port_setup_hose()
1945 out_le32(mbase + 0x208, 0x06040001); in ppc4xx_pciex_port_setup_hose()
1951 out_le32(mbase + 0x208, 0x0b200001); in ppc4xx_pciex_port_setup_hose()
2021 port->endpoint = 0; in ppc4xx_probe_pciex_bridge()
2029 if (of_address_to_resource(np, 0, &port->cfg_space)) { in ppc4xx_probe_pciex_bridge()
2040 dcrs = dcr_resource_start(np, 0); in ppc4xx_probe_pciex_bridge()
2041 if (dcrs == 0) { in ppc4xx_probe_pciex_bridge()
2045 port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0)); in ppc4xx_probe_pciex_bridge()
2074 return 0; in ppc4xx_pci_find_bridges()