Lines Matching +full:unit +full:- +full:address
14 #define DCRN_PLB4_P0EARL 0x014 /* PLB0 Error Address Register Low */
15 #define DCRN_PLB4_P0EARH 0x015 /* PLB0 Error Address Register High */
22 #define DCRN_PLB4_P1EARL 0x01C /* PLB1 Error Address Register Low */
23 #define DCRN_PLB4_P1EARH 0x01D /* PLB1 Error Address Register High */
33 #define PLB4OPB_GESR0 0x0 /* Error status 0: Master Dev 0-3 */
34 #define PLB4OPB_GEAR 0x2 /* Error Address Register */
35 #define PLB4OPB_GEARU 0x3 /* Error Upper Address Register */
36 #define PLB4OPB_GESR1 0x4 /* Error Status 1: Master Dev 4-7 */
37 #define PLB4OPB_GESR2 0xC /* Error Status 2: Master Dev 8-11 */
39 /* PLB4-to-AHB Bridge */
54 /* PLB4-to-PLB6 Bridge */
60 /* PLB6-to-PLB4 Bridge */
66 /* PLB6-to-MCIF Bridge */
164 /* PLB-Attached DDR3/4 Core Wrapper */
196 #define CMUN_URCR3_RS 0x24 /* Unit Reset Control Reg 3 Set */
197 #define CMUN_URCR3_C 0x25 /* Unit Reset Control Reg 3 Clear */
198 #define CMUN_URCR3_P 0x26 /* Unit Reset Control Reg 3 Pulse */
200 #define CMUN_URCR0_P 0x2D /* Unit Reset Control Reg 0 Pulse */
201 #define CMUN_URCR1_P 0x2E /* Unit Reset Control Reg 1 Pulse */
202 #define CMUN_URCR2_P 0x2F /* Unit Reset Control Reg 2 Pulse */
206 #define CMUN_URCR2_RS 0x33 /* Unit Reset Control Reg 2 Set */
207 #define CMUN_URCR2_C 0x34 /* Unit Reset Control Reg 2 Clear */