Lines Matching +full:word +full:- +full:size
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Single-step support.
70 * Emulate the truncation of 64 bit values in 32-bit mode.
92 op->type |= DECCTR; in branch_taken()
93 if (((bo >> 1) & 1) ^ (regs->ctr == 1)) in branch_taken()
99 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1)) in branch_taken()
114 regs->dar = TASK_SIZE_MAX - 1; in address_ok()
116 regs->dar = ea; in address_ok()
121 * Calculate effective address for a D-form instruction
130 ea = (signed short) instr; /* sign-extend */ in dform_ea()
132 ea += regs->gpr[ra]; in dform_ea()
139 * Calculate effective address for a DS-form instruction
148 ea = (signed short) (instr & ~3); /* sign-extend */ in dsform_ea()
150 ea += regs->gpr[ra]; in dsform_ea()
156 * Calculate effective address for a DQ-form instruction
165 ea = (signed short) (instr & ~0xf); /* sign-extend */ in dqform_ea()
167 ea += regs->gpr[ra]; in dqform_ea()
174 * Calculate effective address for an X-form instruction
184 ea = regs->gpr[rb]; in xform_ea()
186 ea += regs->gpr[ra]; in xform_ea()
192 * Calculate effective address for a MLS:D-form / 8LS:D-form
218 ea += regs->gpr[ra]; in mlsd_8lsd_ea()
222 ea += regs->nip; in mlsd_8lsd_ea()
239 return x & -x; /* isolates rightmost bit */ in max_align()
325 regs->dar = ea; in __read_mem_aligned()
326 return -EFAULT; in __read_mem_aligned()
341 err = -EFAULT; in read_mem_aligned()
342 regs->dar = ea; in read_mem_aligned()
356 for (; nb > 0; nb -= c) { in __copy_mem_in()
382 regs->dar = ea; in __copy_mem_in()
383 return -EFAULT; in __copy_mem_in()
397 err = -EFAULT; in copy_mem_in()
398 regs->dar = ea; in copy_mem_in()
416 i = IS_BE ? sizeof(unsigned long) - nb : 0; in read_mem_unaligned()
425 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
426 * If nb < sizeof(long), the result is right-justified on BE systems.
432 return -EFAULT; in read_mem()
433 if ((ea & (nb - 1)) == 0) in read_mem()
461 regs->dar = ea; in __write_mem_aligned()
462 return -EFAULT; in __write_mem_aligned()
477 err = -EFAULT; in write_mem_aligned()
478 regs->dar = ea; in write_mem_aligned()
492 for (; nb > 0; nb -= c) { in __copy_mem_out()
518 regs->dar = ea; in __copy_mem_out()
519 return -EFAULT; in __copy_mem_out()
533 err = -EFAULT; in copy_mem_out()
534 regs->dar = ea; in copy_mem_out()
551 i = IS_BE ? sizeof(unsigned long) - nb : 0; in write_mem_unaligned()
557 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
563 return -EFAULT; in write_mem()
564 if ((ea & (nb - 1)) == 0) in write_mem()
573 * thread_struct, depending on regs->msr & MSR_FP.
588 nb = GETSIZE(op->type); in do_fp_load()
590 return -EINVAL; in do_fp_load()
592 return -EFAULT; in do_fp_load()
593 rn = op->reg; in do_fp_load()
604 if (op->type & FPCONV) in do_fp_load()
606 else if (op->type & SIGNEXT) in do_fp_load()
611 if (regs->msr & MSR_FP) in do_fp_load()
614 current->thread.TS_FPR(rn) = u.l[0]; in do_fp_load()
618 if (regs->msr & MSR_FP) in do_fp_load()
621 current->thread.TS_FPR(rn) = u.l[1]; in do_fp_load()
640 nb = GETSIZE(op->type); in do_fp_store()
642 return -EINVAL; in do_fp_store()
644 return -EFAULT; in do_fp_store()
645 rn = op->reg; in do_fp_store()
647 if (regs->msr & MSR_FP) in do_fp_store()
650 u.l[0] = current->thread.TS_FPR(rn); in do_fp_store()
652 if (op->type & FPCONV) in do_fp_store()
659 if (regs->msr & MSR_FP) in do_fp_store()
662 u.l[1] = current->thread.TS_FPR(rn); in do_fp_store()
678 int size, struct pt_regs *regs, in do_vec_load() argument
687 if (size > sizeof(u)) in do_vec_load()
688 return -EINVAL; in do_vec_load()
691 return -EFAULT; in do_vec_load()
692 /* align to multiple of size */ in do_vec_load()
693 ea &= ~(size - 1); in do_vec_load()
694 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs); in do_vec_load()
698 do_byte_reverse(&u.b[ea & 0xf], min_t(size_t, size, sizeof(u))); in do_vec_load()
700 if (regs->msr & MSR_VEC) in do_vec_load()
703 current->thread.vr_state.vr[rn] = u.v; in do_vec_load()
709 int size, struct pt_regs *regs, in do_vec_store() argument
717 if (size > sizeof(u)) in do_vec_store()
718 return -EINVAL; in do_vec_store()
721 return -EFAULT; in do_vec_store()
722 /* align to multiple of size */ in do_vec_store()
723 ea &= ~(size - 1); in do_vec_store()
726 if (regs->msr & MSR_VEC) in do_vec_store()
729 u.v = current->thread.vr_state.vr[rn]; in do_vec_store()
732 do_byte_reverse(&u.b[ea & 0xf], min_t(size_t, size, sizeof(u))); in do_vec_store()
733 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs); in do_vec_store()
744 return -EFAULT; in emulate_lq()
747 err = do_lq(ea, ®s->gpr[reg]); in emulate_lq()
749 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs); in emulate_lq()
751 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs); in emulate_lq()
754 do_byte_reverse(®s->gpr[reg], 16); in emulate_lq()
765 return -EFAULT; in emulate_stq()
766 vals[0] = regs->gpr[reg]; in emulate_stq()
767 vals[1] = regs->gpr[reg + 1]; in emulate_stq()
786 int size, read_size; in emulate_vsx_load() local
792 size = GETSIZE(op->type); in emulate_vsx_load()
793 reg->d[0] = reg->d[1] = 0; in emulate_vsx_load()
795 switch (op->element_size) { in emulate_vsx_load()
800 if (size == 0) in emulate_vsx_load()
802 memcpy(reg, mem, size); in emulate_vsx_load()
803 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) in emulate_vsx_load()
806 do_byte_reverse(reg, size); in emulate_vsx_load()
810 read_size = (size >= 8) ? 8 : size; in emulate_vsx_load()
811 i = IS_LE ? 8 : 8 - read_size; in emulate_vsx_load()
812 memcpy(®->b[i], mem, read_size); in emulate_vsx_load()
814 do_byte_reverse(®->b[i], 8); in emulate_vsx_load()
815 if (size < 8) { in emulate_vsx_load()
816 if (op->type & SIGNEXT) { in emulate_vsx_load()
817 /* size == 4 is the only case here */ in emulate_vsx_load()
818 reg->d[IS_LE] = (signed int) reg->d[IS_LE]; in emulate_vsx_load()
819 } else if (op->vsx_flags & VSX_FPCONV) { in emulate_vsx_load()
821 conv_sp_to_dp(®->fp[1 + IS_LE], in emulate_vsx_load()
822 ®->dp[IS_LE]); in emulate_vsx_load()
826 if (size == 16) { in emulate_vsx_load()
828 reg->d[IS_BE] = !rev ? v : byterev_8(v); in emulate_vsx_load()
829 } else if (op->vsx_flags & VSX_SPLAT) in emulate_vsx_load()
830 reg->d[IS_BE] = reg->d[IS_LE]; in emulate_vsx_load()
836 for (j = 0; j < size / 4; ++j) { in emulate_vsx_load()
837 i = IS_LE ? 3 - j : j; in emulate_vsx_load()
838 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++); in emulate_vsx_load()
840 if (op->vsx_flags & VSX_SPLAT) { in emulate_vsx_load()
841 u32 val = reg->w[IS_LE ? 3 : 0]; in emulate_vsx_load()
843 i = IS_LE ? 3 - j : j; in emulate_vsx_load()
844 reg->w[i] = val; in emulate_vsx_load()
851 for (j = 0; j < size / 2; ++j) { in emulate_vsx_load()
852 i = IS_LE ? 7 - j : j; in emulate_vsx_load()
853 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++); in emulate_vsx_load()
859 for (j = 0; j < size; ++j) { in emulate_vsx_load()
860 i = IS_LE ? 15 - j : j; in emulate_vsx_load()
861 reg->b[i] = *bp++; in emulate_vsx_load()
870 int size, write_size; in emulate_vsx_store() local
877 size = GETSIZE(op->type); in emulate_vsx_store()
879 switch (op->element_size) { in emulate_vsx_store()
882 if (size == 0) in emulate_vsx_store()
891 memcpy(mem, buf32, size); in emulate_vsx_store()
893 memcpy(mem, reg, size); in emulate_vsx_store()
898 if (size == 0) in emulate_vsx_store()
900 if (IS_LE && (op->vsx_flags & VSX_LDLEFT)) in emulate_vsx_store()
904 buf.d[0] = byterev_8(reg->d[1]); in emulate_vsx_store()
905 buf.d[1] = byterev_8(reg->d[0]); in emulate_vsx_store()
908 memcpy(mem, reg, size); in emulate_vsx_store()
912 write_size = (size >= 8) ? 8 : size; in emulate_vsx_store()
913 i = IS_LE ? 8 : 8 - write_size; in emulate_vsx_store()
914 if (size < 8 && op->vsx_flags & VSX_FPCONV) { in emulate_vsx_store()
917 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]); in emulate_vsx_store()
921 memcpy(mem, ®->b[i], write_size); in emulate_vsx_store()
922 if (size == 16) in emulate_vsx_store()
923 memcpy(mem + 8, ®->d[IS_BE], 8); in emulate_vsx_store()
926 if (size == 16) in emulate_vsx_store()
933 for (j = 0; j < size / 4; ++j) { in emulate_vsx_store()
934 i = IS_LE ? 3 - j : j; in emulate_vsx_store()
935 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]); in emulate_vsx_store()
941 for (j = 0; j < size / 2; ++j) { in emulate_vsx_store()
942 i = IS_LE ? 7 - j : j; in emulate_vsx_store()
943 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]); in emulate_vsx_store()
949 for (j = 0; j < size; ++j) { in emulate_vsx_store()
950 i = IS_LE ? 15 - j : j; in emulate_vsx_store()
951 *bp++ = reg->b[i]; in emulate_vsx_store()
961 int reg = op->reg; in do_vsx_load()
965 int size = GETSIZE(op->type); in do_vsx_load() local
967 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs)) in do_vsx_load()
968 return -EFAULT; in do_vsx_load()
970 nr_vsx_regs = max(1ul, size / sizeof(__vector128)); in do_vsx_load()
975 if (regs->msr & MSR_FP) { in do_vsx_load()
977 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_load()
982 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_load()
983 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0]; in do_vsx_load()
984 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1]; in do_vsx_load()
988 if (regs->msr & MSR_VEC) { in do_vsx_load()
990 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_load()
995 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_load()
996 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v; in do_vsx_load()
1008 int reg = op->reg; in do_vsx_store()
1012 int size = GETSIZE(op->type); in do_vsx_store() local
1014 if (!address_ok(regs, ea, size)) in do_vsx_store()
1015 return -EFAULT; in do_vsx_store()
1017 nr_vsx_regs = max(1ul, size / sizeof(__vector128)); in do_vsx_store()
1021 if (regs->msr & MSR_FP) { in do_vsx_store()
1023 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_store()
1028 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_store()
1029 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0]; in do_vsx_store()
1030 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1]; in do_vsx_store()
1034 if (regs->msr & MSR_VEC) { in do_vsx_store()
1036 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_store()
1041 j = IS_LE ? nr_vsx_regs - i - 1 : i; in do_vsx_store()
1042 buf[j].v = current->thread.vr_state.vr[reg - 32 + i]; in do_vsx_store()
1048 return copy_mem_out(mem, ea, size, regs); in do_vsx_store()
1055 unsigned long size = l1_dcache_bytes(); in __emulate_dcbz() local
1057 for (i = 0; i < size; i += sizeof(long)) in __emulate_dcbz()
1063 return -EFAULT; in __emulate_dcbz()
1069 unsigned long size = l1_dcache_bytes(); in emulate_dcbz() local
1071 ea = truncate_if_32bit(regs->msr, ea); in emulate_dcbz()
1072 ea &= ~(size - 1); in emulate_dcbz()
1073 if (!address_ok(regs, ea, size)) in emulate_dcbz()
1074 return -EFAULT; in emulate_dcbz()
1078 } else if (user_write_access_begin((void __user *)ea, size)) { in emulate_dcbz()
1082 err = -EFAULT; in emulate_dcbz()
1086 regs->dar = ea; in emulate_dcbz()
1107 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1122 : "r" (addr), "i" (-EFAULT), "0" (err))
1134 : "r" (addr), "i" (-EFAULT), "0" (err))
1139 long val = op->val; in set_cr0()
1141 op->type |= SETCC; in set_cr0()
1142 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000); in set_cr0()
1143 if (!(regs->msr & MSR_64BIT)) in set_cr0()
1146 op->ccval |= 0x80000000; in set_cr0()
1148 op->ccval |= 0x40000000; in set_cr0()
1150 op->ccval |= 0x20000000; in set_cr0()
1157 op->xerval |= XER_CA32; in set_ca32()
1159 op->xerval &= ~XER_CA32; in set_ca32()
1172 op->type = COMPUTE | SETREG | SETXER; in add_with_carry()
1173 op->reg = rd; in add_with_carry()
1174 op->val = val; in add_with_carry()
1175 val = truncate_if_32bit(regs->msr, val); in add_with_carry()
1176 val1 = truncate_if_32bit(regs->msr, val1); in add_with_carry()
1177 op->xerval = regs->xer; in add_with_carry()
1179 op->xerval |= XER_CA; in add_with_carry()
1181 op->xerval &= ~XER_CA; in add_with_carry()
1193 op->type = COMPUTE | SETCC; in do_cmp_signed()
1194 crval = (regs->xer >> 31) & 1; /* get SO bit */ in do_cmp_signed()
1201 shift = (7 - crfld) * 4; in do_cmp_signed()
1202 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); in do_cmp_signed()
1212 op->type = COMPUTE | SETCC; in do_cmp_unsigned()
1213 crval = (regs->xer >> 31) & 1; /* get SO bit */ in do_cmp_unsigned()
1220 shift = (7 - crfld) * 4; in do_cmp_unsigned()
1221 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift); in do_cmp_unsigned()
1237 op->val = out_val; in do_cmpb()
1241 * The size parameter is used to adjust the equivalent popcnt instruction.
1246 unsigned long v1, int size) in do_popcnt() argument
1250 out -= (out >> 1) & 0x5555555555555555ULL; in do_popcnt()
1255 if (size == 8) { /* popcntb */ in do_popcnt()
1256 op->val = out; in do_popcnt()
1261 if (size == 32) { /* popcntw */ in do_popcnt()
1262 op->val = out & 0x0000003f0000003fULL; in do_popcnt()
1267 op->val = out; /* popcntd */ in do_popcnt()
1285 op->val = perm; in do_bpermd()
1289 * The size parameter adjusts the equivalent prty instruction.
1294 unsigned long v, int size) in do_prty() argument
1299 if (size == 32) { /* prtyw */ in do_prty()
1300 op->val = res & 0x0000000100000001ULL; in do_prty()
1305 op->val = res & 1; /*prtyd */ in do_prty()
1326 * Elements of 32-bit rotate and mask instructions.
1329 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1332 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1338 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1347 * updating *regs with the information in *op, -1 if we need the
1361 unsigned int word, suffix; in analyse_instr() local
1364 word = ppc_inst_val(instr); in analyse_instr()
1367 op->type = COMPUTE; in analyse_instr()
1372 op->type = BRANCH; in analyse_instr()
1373 imm = (signed short)(word & 0xfffc); in analyse_instr()
1374 if ((word & 2) == 0) in analyse_instr()
1375 imm += regs->nip; in analyse_instr()
1376 op->val = truncate_if_32bit(regs->msr, imm); in analyse_instr()
1377 if (word & 1) in analyse_instr()
1378 op->type |= SETLK; in analyse_instr()
1379 if (branch_taken(word, regs, op)) in analyse_instr()
1380 op->type |= BRTAKEN; in analyse_instr()
1383 if ((word & 0xfe2) == 2) in analyse_instr()
1384 op->type = SYSCALL; in analyse_instr()
1386 (word & 0xfe3) == 1) { /* scv */ in analyse_instr()
1387 op->type = SYSCALL_VECTORED_0; in analyse_instr()
1391 op->type = UNKNOWN; in analyse_instr()
1394 op->type = BRANCH | BRTAKEN; in analyse_instr()
1395 imm = word & 0x03fffffc; in analyse_instr()
1397 imm -= 0x04000000; in analyse_instr()
1398 if ((word & 2) == 0) in analyse_instr()
1399 imm += regs->nip; in analyse_instr()
1400 op->val = truncate_if_32bit(regs->msr, imm); in analyse_instr()
1401 if (word & 1) in analyse_instr()
1402 op->type |= SETLK; in analyse_instr()
1405 switch ((word >> 1) & 0x3ff) { in analyse_instr()
1407 op->type = COMPUTE + SETCC; in analyse_instr()
1408 rd = 7 - ((word >> 23) & 0x7); in analyse_instr()
1409 ra = 7 - ((word >> 18) & 0x7); in analyse_instr()
1412 val = (regs->ccr >> ra) & 0xf; in analyse_instr()
1413 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd); in analyse_instr()
1418 op->type = BRANCH; in analyse_instr()
1419 imm = (word & 0x400)? regs->ctr: regs->link; in analyse_instr()
1420 op->val = truncate_if_32bit(regs->msr, imm); in analyse_instr()
1421 if (word & 1) in analyse_instr()
1422 op->type |= SETLK; in analyse_instr()
1423 if (branch_taken(word, regs, op)) in analyse_instr()
1424 op->type |= BRTAKEN; in analyse_instr()
1430 op->type = RFI; in analyse_instr()
1434 op->type = BARRIER | BARRIER_ISYNC; in analyse_instr()
1445 op->type = COMPUTE + SETCC; in analyse_instr()
1446 ra = (word >> 16) & 0x1f; in analyse_instr()
1447 rb = (word >> 11) & 0x1f; in analyse_instr()
1448 rd = (word >> 21) & 0x1f; in analyse_instr()
1449 ra = (regs->ccr >> (31 - ra)) & 1; in analyse_instr()
1450 rb = (regs->ccr >> (31 - rb)) & 1; in analyse_instr()
1451 val = (word >> (6 + ra * 2 + rb)) & 1; in analyse_instr()
1452 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) | in analyse_instr()
1453 (val << (31 - rd)); in analyse_instr()
1458 switch ((word >> 1) & 0x3ff) { in analyse_instr()
1460 op->type = BARRIER + BARRIER_SYNC; in analyse_instr()
1462 switch ((word >> 21) & 3) { in analyse_instr()
1464 op->type = BARRIER + BARRIER_LWSYNC; in analyse_instr()
1467 op->type = BARRIER + BARRIER_PTESYNC; in analyse_instr()
1474 op->type = BARRIER + BARRIER_EIEIO; in analyse_instr()
1480 rd = (word >> 21) & 0x1f; in analyse_instr()
1481 ra = (word >> 16) & 0x1f; in analyse_instr()
1482 rb = (word >> 11) & 0x1f; in analyse_instr()
1483 rc = (word >> 6) & 0x1f; in analyse_instr()
1491 prefix_r = GET_PREFIX_R(word); in analyse_instr()
1494 op->reg = rd; in analyse_instr()
1495 op->val = regs->gpr[rd]; in analyse_instr()
1497 prefixtype = (word >> 24) & 0x3; in analyse_instr()
1504 op->type = COMPUTE | PREFIXED; in analyse_instr()
1505 op->val = mlsd_8lsd_ea(word, suffix, regs); in analyse_instr()
1511 if (rd & trap_compare(regs->gpr[ra], (short) word)) in analyse_instr()
1516 if (rd & trap_compare((int)regs->gpr[ra], (short) word)) in analyse_instr()
1530 switch (word & 0x3f) { in analyse_instr()
1533 "=r" (op->val) : "r" (regs->gpr[ra]), in analyse_instr()
1534 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); in analyse_instr()
1539 "=r" (op->val) : "r" (regs->gpr[ra]), in analyse_instr()
1540 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); in analyse_instr()
1545 "=r" (op->val) : "r" (regs->gpr[ra]), in analyse_instr()
1546 "r" (regs->gpr[rb]), "r" (regs->gpr[rc])); in analyse_instr()
1558 op->val = regs->gpr[ra] * (short) word; in analyse_instr()
1562 imm = (short) word; in analyse_instr()
1563 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1); in analyse_instr()
1567 imm = (unsigned short) word; in analyse_instr()
1568 val = regs->gpr[ra]; in analyse_instr()
1577 imm = (short) word; in analyse_instr()
1578 val = regs->gpr[ra]; in analyse_instr()
1587 imm = (short) word; in analyse_instr()
1588 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); in analyse_instr()
1592 imm = (short) word; in analyse_instr()
1593 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0); in analyse_instr()
1598 imm = (short) word; in analyse_instr()
1600 imm += regs->gpr[ra]; in analyse_instr()
1601 op->val = imm; in analyse_instr()
1605 imm = ((short) word) << 16; in analyse_instr()
1607 imm += regs->gpr[ra]; in analyse_instr()
1608 op->val = imm; in analyse_instr()
1612 if (((word >> 1) & 0x1f) == 2) { in analyse_instr()
1616 imm = (short) (word & 0xffc1); /* d0 + d2 fields */ in analyse_instr()
1617 imm |= (word >> 15) & 0x3e; /* d1 field */ in analyse_instr()
1618 op->val = regs->nip + (imm << 16) + 4; in analyse_instr()
1621 op->type = UNKNOWN; in analyse_instr()
1625 mb = (word >> 6) & 0x1f; in analyse_instr()
1626 me = (word >> 1) & 0x1f; in analyse_instr()
1627 val = DATA32(regs->gpr[rd]); in analyse_instr()
1629 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm); in analyse_instr()
1633 mb = (word >> 6) & 0x1f; in analyse_instr()
1634 me = (word >> 1) & 0x1f; in analyse_instr()
1635 val = DATA32(regs->gpr[rd]); in analyse_instr()
1636 op->val = ROTATE(val, rb) & MASK32(mb, me); in analyse_instr()
1640 mb = (word >> 6) & 0x1f; in analyse_instr()
1641 me = (word >> 1) & 0x1f; in analyse_instr()
1642 rb = regs->gpr[rb] & 0x1f; in analyse_instr()
1643 val = DATA32(regs->gpr[rd]); in analyse_instr()
1644 op->val = ROTATE(val, rb) & MASK32(mb, me); in analyse_instr()
1648 op->val = regs->gpr[rd] | (unsigned short) word; in analyse_instr()
1652 imm = (unsigned short) word; in analyse_instr()
1653 op->val = regs->gpr[rd] | (imm << 16); in analyse_instr()
1657 op->val = regs->gpr[rd] ^ (unsigned short) word; in analyse_instr()
1661 imm = (unsigned short) word; in analyse_instr()
1662 op->val = regs->gpr[rd] ^ (imm << 16); in analyse_instr()
1666 op->val = regs->gpr[rd] & (unsigned short) word; in analyse_instr()
1671 imm = (unsigned short) word; in analyse_instr()
1672 op->val = regs->gpr[rd] & (imm << 16); in analyse_instr()
1678 mb = ((word >> 6) & 0x1f) | (word & 0x20); in analyse_instr()
1679 val = regs->gpr[rd]; in analyse_instr()
1680 if ((word & 0x10) == 0) { in analyse_instr()
1681 sh = rb | ((word & 2) << 4); in analyse_instr()
1683 switch ((word >> 2) & 3) { in analyse_instr()
1691 val &= MASK64(mb, 63 - sh); in analyse_instr()
1694 imm = MASK64(mb, 63 - sh); in analyse_instr()
1695 val = (regs->gpr[ra] & ~imm) | in analyse_instr()
1698 op->val = val; in analyse_instr()
1701 sh = regs->gpr[rb] & 0x3f; in analyse_instr()
1703 switch ((word >> 1) & 7) { in analyse_instr()
1705 op->val = val & MASK64_L(mb); in analyse_instr()
1708 op->val = val & MASK64_R(mb); in analyse_instr()
1713 op->type = UNKNOWN; /* illegal instruction */ in analyse_instr()
1718 if (((word >> 1) & 0x1f) == 15) { in analyse_instr()
1719 mb = (word >> 6) & 0x1f; /* bc field */ in analyse_instr()
1720 val = (regs->ccr >> (31 - mb)) & 1; in analyse_instr()
1721 val2 = (ra) ? regs->gpr[ra] : 0; in analyse_instr()
1723 op->val = (val) ? val2 : regs->gpr[rb]; in analyse_instr()
1727 switch ((word >> 1) & 0x3ff) { in analyse_instr()
1730 (rd & trap_compare((int)regs->gpr[ra], in analyse_instr()
1731 (int)regs->gpr[rb]))) in analyse_instr()
1736 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb])) in analyse_instr()
1743 op->type = MFMSR; in analyse_instr()
1744 op->reg = rd; in analyse_instr()
1749 op->type = MTMSR; in analyse_instr()
1750 op->reg = rd; in analyse_instr()
1751 op->val = 0xffffffff & ~(MSR_ME | MSR_LE); in analyse_instr()
1757 op->type = MTMSR; in analyse_instr()
1758 op->reg = rd; in analyse_instr()
1761 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL; in analyse_instr()
1762 op->val = imm; in analyse_instr()
1768 if ((word >> 20) & 1) { in analyse_instr()
1771 if (word & (0x80000 >> sh)) in analyse_instr()
1776 op->val = regs->ccr & imm; in analyse_instr()
1790 val = regs->ccr >> (CR0_SHIFT - ra); in analyse_instr()
1793 op->val = -1; in analyse_instr()
1796 op->val = 1; in analyse_instr()
1798 op->val = 0; in analyse_instr()
1802 op->type = COMPUTE + SETCC; in analyse_instr()
1804 val = regs->gpr[rd]; in analyse_instr()
1805 op->ccval = regs->ccr; in analyse_instr()
1807 if (word & (0x80000 >> sh)) in analyse_instr()
1808 op->ccval = (op->ccval & ~imm) | in analyse_instr()
1815 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); in analyse_instr()
1816 op->type = MFSPR; in analyse_instr()
1817 op->reg = rd; in analyse_instr()
1818 op->spr = spr; in analyse_instr()
1825 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0); in analyse_instr()
1826 op->type = MTSPR; in analyse_instr()
1827 op->val = regs->gpr[rd]; in analyse_instr()
1828 op->spr = spr; in analyse_instr()
1838 val = regs->gpr[ra]; in analyse_instr()
1839 val2 = regs->gpr[rb]; in analyse_instr()
1842 /* word (32-bit) compare */ in analyse_instr()
1851 val = regs->gpr[ra]; in analyse_instr()
1852 val2 = regs->gpr[rb]; in analyse_instr()
1855 /* word (32-bit) compare */ in analyse_instr()
1864 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]); in analyse_instr()
1871 add_with_carry(regs, op, rd, ~regs->gpr[ra], in analyse_instr()
1872 regs->gpr[rb], 1); in analyse_instr()
1876 asm("mulhdu %0,%1,%2" : "=r" (op->val) : in analyse_instr()
1877 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); in analyse_instr()
1881 add_with_carry(regs, op, rd, regs->gpr[ra], in analyse_instr()
1882 regs->gpr[rb], 0); in analyse_instr()
1886 asm("mulhwu %0,%1,%2" : "=r" (op->val) : in analyse_instr()
1887 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); in analyse_instr()
1891 op->val = regs->gpr[rb] - regs->gpr[ra]; in analyse_instr()
1895 asm("mulhd %0,%1,%2" : "=r" (op->val) : in analyse_instr()
1896 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); in analyse_instr()
1900 asm("mulhw %0,%1,%2" : "=r" (op->val) : in analyse_instr()
1901 "r" (regs->gpr[ra]), "r" (regs->gpr[rb])); in analyse_instr()
1905 op->val = -regs->gpr[ra]; in analyse_instr()
1909 add_with_carry(regs, op, rd, ~regs->gpr[ra], in analyse_instr()
1910 regs->gpr[rb], regs->xer & XER_CA); in analyse_instr()
1914 add_with_carry(regs, op, rd, regs->gpr[ra], in analyse_instr()
1915 regs->gpr[rb], regs->xer & XER_CA); in analyse_instr()
1919 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L, in analyse_instr()
1920 regs->xer & XER_CA); in analyse_instr()
1924 add_with_carry(regs, op, rd, regs->gpr[ra], 0L, in analyse_instr()
1925 regs->xer & XER_CA); in analyse_instr()
1929 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L, in analyse_instr()
1930 regs->xer & XER_CA); in analyse_instr()
1934 op->val = regs->gpr[ra] * regs->gpr[rb]; in analyse_instr()
1938 add_with_carry(regs, op, rd, regs->gpr[ra], -1L, in analyse_instr()
1939 regs->xer & XER_CA); in analyse_instr()
1943 op->val = (long)(int) regs->gpr[ra] * in analyse_instr()
1944 (int) regs->gpr[rb]; in analyse_instr()
1951 op->val = regs->gpr[ra] % regs->gpr[rb]; in analyse_instr()
1955 op->val = regs->gpr[ra] + regs->gpr[rb]; in analyse_instr()
1961 op->val = (unsigned int) regs->gpr[ra] % in analyse_instr()
1962 (unsigned int) regs->gpr[rb]; in analyse_instr()
1966 op->val = regs->gpr[ra] / regs->gpr[rb]; in analyse_instr()
1970 op->val = (unsigned int) regs->gpr[ra] / in analyse_instr()
1971 (unsigned int) regs->gpr[rb]; in analyse_instr()
1975 op->val = (long int) regs->gpr[ra] / in analyse_instr()
1976 (long int) regs->gpr[rb]; in analyse_instr()
1980 op->val = (int) regs->gpr[ra] / in analyse_instr()
1981 (int) regs->gpr[rb]; in analyse_instr()
1986 "=r" (op->val) : "r" (regs->gpr[ra]), in analyse_instr()
1987 "r" (regs->gpr[rb])); in analyse_instr()
1991 "=r" (op->val) : "r" (regs->gpr[ra]), in analyse_instr()
1992 "r" (regs->gpr[rb])); in analyse_instr()
2000 /* 32-bit conditioned */ in analyse_instr()
2001 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val)); in analyse_instr()
2005 /* 64-bit conditioned */ in analyse_instr()
2006 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val)); in analyse_instr()
2010 /* 64-bit raw */ in analyse_instr()
2011 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val)); in analyse_instr()
2020 op->val = (long int) regs->gpr[ra] % in analyse_instr()
2021 (long int) regs->gpr[rb]; in analyse_instr()
2027 op->val = (int) regs->gpr[ra] % in analyse_instr()
2028 (int) regs->gpr[rb]; in analyse_instr()
2036 val = (unsigned int) regs->gpr[rd]; in analyse_instr()
2037 op->val = ( val ? __builtin_clz(val) : 32 ); in analyse_instr()
2041 val = regs->gpr[rd]; in analyse_instr()
2042 op->val = ( val ? __builtin_clzl(val) : 64 ); in analyse_instr()
2046 op->val = regs->gpr[rd] & regs->gpr[rb]; in analyse_instr()
2050 op->val = regs->gpr[rd] & ~regs->gpr[rb]; in analyse_instr()
2054 do_popcnt(regs, op, regs->gpr[rd], 8); in analyse_instr()
2058 op->val = ~(regs->gpr[rd] | regs->gpr[rb]); in analyse_instr()
2062 do_prty(regs, op, regs->gpr[rd], 32); in analyse_instr()
2066 do_prty(regs, op, regs->gpr[rd], 64); in analyse_instr()
2070 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]); in analyse_instr()
2074 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]); in analyse_instr()
2078 op->val = regs->gpr[rd] ^ regs->gpr[rb]; in analyse_instr()
2082 do_popcnt(regs, op, regs->gpr[rd], 32); in analyse_instr()
2086 op->val = regs->gpr[rd] | ~regs->gpr[rb]; in analyse_instr()
2090 op->val = regs->gpr[rd] | regs->gpr[rb]; in analyse_instr()
2094 op->val = ~(regs->gpr[rd] & regs->gpr[rb]); in analyse_instr()
2098 do_popcnt(regs, op, regs->gpr[rd], 64); in analyse_instr()
2104 val = (unsigned int) regs->gpr[rd]; in analyse_instr()
2105 op->val = (val ? __builtin_ctz(val) : 32); in analyse_instr()
2111 val = regs->gpr[rd]; in analyse_instr()
2112 op->val = (val ? __builtin_ctzl(val) : 64); in analyse_instr()
2116 op->val = (signed short) regs->gpr[rd]; in analyse_instr()
2120 op->val = (signed char) regs->gpr[rd]; in analyse_instr()
2124 op->val = (signed int) regs->gpr[rd]; in analyse_instr()
2132 sh = regs->gpr[rb] & 0x3f; in analyse_instr()
2134 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL; in analyse_instr()
2136 op->val = 0; in analyse_instr()
2140 sh = regs->gpr[rb] & 0x3f; in analyse_instr()
2142 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh; in analyse_instr()
2144 op->val = 0; in analyse_instr()
2148 op->type = COMPUTE + SETREG + SETXER; in analyse_instr()
2149 sh = regs->gpr[rb] & 0x3f; in analyse_instr()
2150 ival = (signed int) regs->gpr[rd]; in analyse_instr()
2151 op->val = ival >> (sh < 32 ? sh : 31); in analyse_instr()
2152 op->xerval = regs->xer; in analyse_instr()
2153 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0)) in analyse_instr()
2154 op->xerval |= XER_CA; in analyse_instr()
2156 op->xerval &= ~XER_CA; in analyse_instr()
2157 set_ca32(op, op->xerval & XER_CA); in analyse_instr()
2161 op->type = COMPUTE + SETREG + SETXER; in analyse_instr()
2163 ival = (signed int) regs->gpr[rd]; in analyse_instr()
2164 op->val = ival >> sh; in analyse_instr()
2165 op->xerval = regs->xer; in analyse_instr()
2166 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) in analyse_instr()
2167 op->xerval |= XER_CA; in analyse_instr()
2169 op->xerval &= ~XER_CA; in analyse_instr()
2170 set_ca32(op, op->xerval & XER_CA); in analyse_instr()
2175 sh = regs->gpr[rb] & 0x7f; in analyse_instr()
2177 op->val = regs->gpr[rd] << sh; in analyse_instr()
2179 op->val = 0; in analyse_instr()
2183 sh = regs->gpr[rb] & 0x7f; in analyse_instr()
2185 op->val = regs->gpr[rd] >> sh; in analyse_instr()
2187 op->val = 0; in analyse_instr()
2191 op->type = COMPUTE + SETREG + SETXER; in analyse_instr()
2192 sh = regs->gpr[rb] & 0x7f; in analyse_instr()
2193 ival = (signed long int) regs->gpr[rd]; in analyse_instr()
2194 op->val = ival >> (sh < 64 ? sh : 63); in analyse_instr()
2195 op->xerval = regs->xer; in analyse_instr()
2196 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0)) in analyse_instr()
2197 op->xerval |= XER_CA; in analyse_instr()
2199 op->xerval &= ~XER_CA; in analyse_instr()
2200 set_ca32(op, op->xerval & XER_CA); in analyse_instr()
2205 op->type = COMPUTE + SETREG + SETXER; in analyse_instr()
2206 sh = rb | ((word & 2) << 4); in analyse_instr()
2207 ival = (signed long int) regs->gpr[rd]; in analyse_instr()
2208 op->val = ival >> sh; in analyse_instr()
2209 op->xerval = regs->xer; in analyse_instr()
2210 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0) in analyse_instr()
2211 op->xerval |= XER_CA; in analyse_instr()
2213 op->xerval &= ~XER_CA; in analyse_instr()
2214 set_ca32(op, op->xerval & XER_CA); in analyse_instr()
2221 op->type = COMPUTE + SETREG; in analyse_instr()
2222 sh = rb | ((word & 2) << 4); in analyse_instr()
2223 val = (signed int) regs->gpr[rd]; in analyse_instr()
2225 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh); in analyse_instr()
2227 op->val = val; in analyse_instr()
2236 op->type = MKOP(CACHEOP, DCBST, 0); in analyse_instr()
2237 op->ea = xform_ea(word, regs); in analyse_instr()
2241 op->type = MKOP(CACHEOP, DCBF, 0); in analyse_instr()
2242 op->ea = xform_ea(word, regs); in analyse_instr()
2246 op->type = MKOP(CACHEOP, DCBTST, 0); in analyse_instr()
2247 op->ea = xform_ea(word, regs); in analyse_instr()
2248 op->reg = rd; in analyse_instr()
2252 op->type = MKOP(CACHEOP, DCBTST, 0); in analyse_instr()
2253 op->ea = xform_ea(word, regs); in analyse_instr()
2254 op->reg = rd; in analyse_instr()
2258 op->type = MKOP(CACHEOP, ICBI, 0); in analyse_instr()
2259 op->ea = xform_ea(word, regs); in analyse_instr()
2263 op->type = MKOP(CACHEOP, DCBZ, 0); in analyse_instr()
2264 op->ea = xform_ea(word, regs); in analyse_instr()
2273 op->type = UNKNOWN; in analyse_instr()
2274 op->update_reg = ra; in analyse_instr()
2275 op->reg = rd; in analyse_instr()
2276 op->val = regs->gpr[rd]; in analyse_instr()
2277 u = (word >> 20) & UPDATE; in analyse_instr()
2278 op->vsx_flags = 0; in analyse_instr()
2282 u = word & UPDATE; in analyse_instr()
2283 op->ea = xform_ea(word, regs); in analyse_instr()
2284 switch ((word >> 1) & 0x3ff) { in analyse_instr()
2286 op->type = MKOP(LARX, 0, 4); in analyse_instr()
2290 op->type = MKOP(STCX, 0, 4); in analyse_instr()
2295 op->type = MKOP(LARX, 0, 1); in analyse_instr()
2299 op->type = MKOP(STCX, 0, 1); in analyse_instr()
2303 op->type = MKOP(LARX, 0, 2); in analyse_instr()
2307 op->type = MKOP(STCX, 0, 2); in analyse_instr()
2312 op->type = MKOP(LARX, 0, 8); in analyse_instr()
2316 op->type = MKOP(STCX, 0, 8); in analyse_instr()
2321 op->type = MKOP(LARX, 0, 16); in analyse_instr()
2326 op->type = MKOP(STCX, 0, 16); in analyse_instr()
2332 op->type = MKOP(LOAD, u, 4); in analyse_instr()
2337 op->type = MKOP(LOAD, u, 1); in analyse_instr()
2346 op->type = MKOP(LOAD_VMX, 0, 1); in analyse_instr()
2347 op->element_size = 1; in analyse_instr()
2351 op->type = MKOP(LOAD_VMX, 0, 2); in analyse_instr()
2352 op->element_size = 2; in analyse_instr()
2356 op->type = MKOP(LOAD_VMX, 0, 4); in analyse_instr()
2357 op->element_size = 4; in analyse_instr()
2362 op->type = MKOP(LOAD_VMX, 0, 16); in analyse_instr()
2363 op->element_size = 16; in analyse_instr()
2367 op->type = MKOP(STORE_VMX, 0, 1); in analyse_instr()
2368 op->element_size = 1; in analyse_instr()
2372 op->type = MKOP(STORE_VMX, 0, 2); in analyse_instr()
2373 op->element_size = 2; in analyse_instr()
2377 op->type = MKOP(STORE_VMX, 0, 4); in analyse_instr()
2378 op->element_size = 4; in analyse_instr()
2383 op->type = MKOP(STORE_VMX, 0, 16); in analyse_instr()
2390 op->type = MKOP(LOAD, u, 8); in analyse_instr()
2395 op->type = MKOP(STORE, u, 8); in analyse_instr()
2401 op->type = MKOP(STORE, u, 4); in analyse_instr()
2406 op->type = MKOP(STORE, u, 1); in analyse_instr()
2411 op->type = MKOP(LOAD, u, 2); in analyse_instr()
2417 op->type = MKOP(LOAD, SIGNEXT | u, 4); in analyse_instr()
2423 op->type = MKOP(LOAD, SIGNEXT | u, 2); in analyse_instr()
2428 op->type = MKOP(STORE, u, 2); in analyse_instr()
2433 op->type = MKOP(LOAD, BYTEREV, 8); in analyse_instr()
2438 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f); in analyse_instr()
2442 op->type = MKOP(LOAD, BYTEREV, 4); in analyse_instr()
2448 op->type = MKOP(LOAD_MULTI, 0, rb); in analyse_instr()
2449 op->ea = ra ? regs->gpr[ra] : 0; in analyse_instr()
2455 op->type = MKOP(LOAD_FP, u | FPCONV, 4); in analyse_instr()
2460 op->type = MKOP(LOAD_FP, u, 8); in analyse_instr()
2465 op->type = MKOP(STORE_FP, u | FPCONV, 4); in analyse_instr()
2470 op->type = MKOP(STORE_FP, u, 8); in analyse_instr()
2475 op->type = MKOP(LOAD_FP, 0, 16); in analyse_instr()
2479 op->type = MKOP(LOAD_FP, SIGNEXT, 4); in analyse_instr()
2483 op->type = MKOP(LOAD_FP, 0, 4); in analyse_instr()
2487 op->type = MKOP(STORE_FP, 0, 16); in analyse_instr()
2491 op->type = MKOP(STORE_FP, 0, 4); in analyse_instr()
2498 op->type = MKOP(STORE, BYTEREV, 8); in analyse_instr()
2499 op->val = byterev_8(regs->gpr[rd]); in analyse_instr()
2504 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f); in analyse_instr()
2508 op->type = MKOP(STORE, BYTEREV, 4); in analyse_instr()
2509 op->val = byterev_4(regs->gpr[rd]); in analyse_instr()
2515 op->type = MKOP(STORE_MULTI, 0, rb); in analyse_instr()
2516 op->ea = ra ? regs->gpr[ra] : 0; in analyse_instr()
2520 op->type = MKOP(LOAD, BYTEREV, 2); in analyse_instr()
2524 op->type = MKOP(STORE, BYTEREV, 2); in analyse_instr()
2525 op->val = byterev_2(regs->gpr[rd]); in analyse_instr()
2530 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2531 op->type = MKOP(LOAD_VSX, 0, 4); in analyse_instr()
2532 op->element_size = 8; in analyse_instr()
2536 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2537 op->type = MKOP(LOAD_VSX, SIGNEXT, 4); in analyse_instr()
2538 op->element_size = 8; in analyse_instr()
2542 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2543 op->type = MKOP(STORE_VSX, 0, 4); in analyse_instr()
2544 op->element_size = 8; in analyse_instr()
2550 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2551 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2552 op->element_size = 16; in analyse_instr()
2553 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2561 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2562 op->ea = ra ? regs->gpr[ra] : 0; in analyse_instr()
2563 nb = regs->gpr[rb] & 0xff; in analyse_instr()
2566 op->type = MKOP(LOAD_VSX, 0, nb); in analyse_instr()
2567 op->element_size = 16; in analyse_instr()
2568 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | in analyse_instr()
2573 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2574 op->type = MKOP(LOAD_VSX, 0, 8); in analyse_instr()
2575 op->element_size = 8; in analyse_instr()
2576 op->vsx_flags = VSX_SPLAT; in analyse_instr()
2582 op->reg = VSX_REGISTER_XTP(rd); in analyse_instr()
2583 op->type = MKOP(LOAD_VSX, 0, 32); in analyse_instr()
2584 op->element_size = 32; in analyse_instr()
2590 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2591 op->type = MKOP(LOAD_VSX, 0, 4); in analyse_instr()
2592 op->element_size = 4; in analyse_instr()
2593 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC; in analyse_instr()
2599 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2600 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2601 op->element_size = 16; in analyse_instr()
2602 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2610 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2611 op->ea = ra ? regs->gpr[ra] : 0; in analyse_instr()
2612 nb = regs->gpr[rb] & 0xff; in analyse_instr()
2615 op->type = MKOP(STORE_VSX, 0, nb); in analyse_instr()
2616 op->element_size = 16; in analyse_instr()
2617 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) | in analyse_instr()
2624 op->reg = VSX_REGISTER_XTP(rd); in analyse_instr()
2625 op->type = MKOP(STORE_VSX, 0, 32); in analyse_instr()
2626 op->element_size = 32; in analyse_instr()
2629 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2630 op->type = MKOP(LOAD_VSX, 0, 4); in analyse_instr()
2631 op->element_size = 8; in analyse_instr()
2632 op->vsx_flags = VSX_FPCONV; in analyse_instr()
2636 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2637 op->type = MKOP(LOAD_VSX, 0, 8); in analyse_instr()
2638 op->element_size = 8; in analyse_instr()
2642 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2643 op->type = MKOP(STORE_VSX, 0, 4); in analyse_instr()
2644 op->element_size = 8; in analyse_instr()
2645 op->vsx_flags = VSX_FPCONV; in analyse_instr()
2649 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2650 op->type = MKOP(STORE_VSX, 0, 8); in analyse_instr()
2651 op->element_size = 8; in analyse_instr()
2655 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2656 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2657 op->element_size = 4; in analyse_instr()
2663 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2664 op->type = MKOP(LOAD_VSX, 0, 1); in analyse_instr()
2665 op->element_size = 8; in analyse_instr()
2666 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2672 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2673 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2674 op->element_size = 2; in analyse_instr()
2675 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2681 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2682 op->type = MKOP(LOAD_VSX, 0, 2); in analyse_instr()
2683 op->element_size = 8; in analyse_instr()
2684 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2688 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2689 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2690 op->element_size = 8; in analyse_instr()
2696 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2697 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2698 op->element_size = 1; in analyse_instr()
2699 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2703 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2704 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2705 op->element_size = 4; in analyse_instr()
2711 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2712 op->type = MKOP(STORE_VSX, 0, 1); in analyse_instr()
2713 op->element_size = 8; in analyse_instr()
2714 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2720 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2721 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2722 op->element_size = 2; in analyse_instr()
2723 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2729 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2730 op->type = MKOP(STORE_VSX, 0, 2); in analyse_instr()
2731 op->element_size = 8; in analyse_instr()
2732 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2736 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2737 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2738 op->element_size = 8; in analyse_instr()
2744 op->reg = rd | ((word & 1) << 5); in analyse_instr()
2745 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2746 op->element_size = 1; in analyse_instr()
2747 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2756 op->type = MKOP(LOAD, u, 4); in analyse_instr()
2757 op->ea = dform_ea(word, regs); in analyse_instr()
2762 op->type = MKOP(LOAD, u, 1); in analyse_instr()
2763 op->ea = dform_ea(word, regs); in analyse_instr()
2768 op->type = MKOP(STORE, u, 4); in analyse_instr()
2769 op->ea = dform_ea(word, regs); in analyse_instr()
2774 op->type = MKOP(STORE, u, 1); in analyse_instr()
2775 op->ea = dform_ea(word, regs); in analyse_instr()
2780 op->type = MKOP(LOAD, u, 2); in analyse_instr()
2781 op->ea = dform_ea(word, regs); in analyse_instr()
2786 op->type = MKOP(LOAD, SIGNEXT | u, 2); in analyse_instr()
2787 op->ea = dform_ea(word, regs); in analyse_instr()
2792 op->type = MKOP(STORE, u, 2); in analyse_instr()
2793 op->ea = dform_ea(word, regs); in analyse_instr()
2799 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd)); in analyse_instr()
2800 op->ea = dform_ea(word, regs); in analyse_instr()
2804 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd)); in analyse_instr()
2805 op->ea = dform_ea(word, regs); in analyse_instr()
2811 op->type = MKOP(LOAD_FP, u | FPCONV, 4); in analyse_instr()
2812 op->ea = dform_ea(word, regs); in analyse_instr()
2817 op->type = MKOP(LOAD_FP, u, 8); in analyse_instr()
2818 op->ea = dform_ea(word, regs); in analyse_instr()
2823 op->type = MKOP(STORE_FP, u | FPCONV, 4); in analyse_instr()
2824 op->ea = dform_ea(word, regs); in analyse_instr()
2829 op->type = MKOP(STORE_FP, u, 8); in analyse_instr()
2830 op->ea = dform_ea(word, regs); in analyse_instr()
2837 op->type = MKOP(LOAD, 0, 16); in analyse_instr()
2838 op->ea = dqform_ea(word, regs); in analyse_instr()
2844 op->ea = dsform_ea(word, regs); in analyse_instr()
2845 switch (word & 3) { in analyse_instr()
2849 op->type = MKOP(LOAD_FP, 0, 16); in analyse_instr()
2854 op->reg = rd + 32; in analyse_instr()
2855 op->type = MKOP(LOAD_VSX, 0, 8); in analyse_instr()
2856 op->element_size = 8; in analyse_instr()
2857 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2862 op->reg = rd + 32; in analyse_instr()
2863 op->type = MKOP(LOAD_VSX, 0, 4); in analyse_instr()
2864 op->element_size = 8; in analyse_instr()
2865 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; in analyse_instr()
2873 op->ea = dsform_ea(word, regs); in analyse_instr()
2874 switch (word & 3) { in analyse_instr()
2876 op->type = MKOP(LOAD, 0, 8); in analyse_instr()
2879 op->type = MKOP(LOAD, UPDATE, 8); in analyse_instr()
2882 op->type = MKOP(LOAD, SIGNEXT, 4); in analyse_instr()
2892 op->ea = dqform_ea(word, regs); in analyse_instr()
2893 op->reg = VSX_REGISTER_XTP(rd); in analyse_instr()
2894 op->element_size = 32; in analyse_instr()
2895 switch (word & 0xf) { in analyse_instr()
2897 op->type = MKOP(LOAD_VSX, 0, 32); in analyse_instr()
2900 op->type = MKOP(STORE_VSX, 0, 32); in analyse_instr()
2906 switch (word & 7) { in analyse_instr()
2909 op->ea = dsform_ea(word, regs); in analyse_instr()
2910 op->type = MKOP(STORE_FP, 0, 16); in analyse_instr()
2916 op->ea = dqform_ea(word, regs); in analyse_instr()
2917 if (word & 8) in analyse_instr()
2918 op->reg = rd + 32; in analyse_instr()
2919 op->type = MKOP(LOAD_VSX, 0, 16); in analyse_instr()
2920 op->element_size = 16; in analyse_instr()
2921 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2928 op->ea = dsform_ea(word, regs); in analyse_instr()
2929 op->reg = rd + 32; in analyse_instr()
2930 op->type = MKOP(STORE_VSX, 0, 8); in analyse_instr()
2931 op->element_size = 8; in analyse_instr()
2932 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2939 op->ea = dsform_ea(word, regs); in analyse_instr()
2940 op->reg = rd + 32; in analyse_instr()
2941 op->type = MKOP(STORE_VSX, 0, 4); in analyse_instr()
2942 op->element_size = 8; in analyse_instr()
2943 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; in analyse_instr()
2949 op->ea = dqform_ea(word, regs); in analyse_instr()
2950 if (word & 8) in analyse_instr()
2951 op->reg = rd + 32; in analyse_instr()
2952 op->type = MKOP(STORE_VSX, 0, 16); in analyse_instr()
2953 op->element_size = 16; in analyse_instr()
2954 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
2962 op->ea = dsform_ea(word, regs); in analyse_instr()
2963 switch (word & 3) { in analyse_instr()
2965 op->type = MKOP(STORE, 0, 8); in analyse_instr()
2968 op->type = MKOP(STORE, UPDATE, 8); in analyse_instr()
2972 op->type = MKOP(STORE, 0, 16); in analyse_instr()
2980 prefix_r = GET_PREFIX_R(word); in analyse_instr()
2982 op->update_reg = ra; in analyse_instr()
2984 op->reg = rd; in analyse_instr()
2985 op->val = regs->gpr[rd]; in analyse_instr()
2988 prefixtype = (word >> 24) & 0x3; in analyse_instr()
2990 case 0: /* Type 00 Eight-Byte Load/Store */ in analyse_instr()
2993 op->ea = mlsd_8lsd_ea(word, suffix, regs); in analyse_instr()
2996 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4); in analyse_instr()
3000 op->reg = rd + 32; in analyse_instr()
3001 op->type = MKOP(LOAD_VSX, PREFIXED, 8); in analyse_instr()
3002 op->element_size = 8; in analyse_instr()
3003 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
3006 op->reg = rd + 32; in analyse_instr()
3007 op->type = MKOP(LOAD_VSX, PREFIXED, 4); in analyse_instr()
3008 op->element_size = 8; in analyse_instr()
3009 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; in analyse_instr()
3012 op->reg = rd + 32; in analyse_instr()
3013 op->type = MKOP(STORE_VSX, PREFIXED, 8); in analyse_instr()
3014 op->element_size = 8; in analyse_instr()
3015 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
3018 op->reg = rd + 32; in analyse_instr()
3019 op->type = MKOP(STORE_VSX, PREFIXED, 4); in analyse_instr()
3020 op->element_size = 8; in analyse_instr()
3021 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC; in analyse_instr()
3024 op->reg += 32; in analyse_instr()
3027 op->type = MKOP(LOAD_VSX, PREFIXED, 16); in analyse_instr()
3028 op->element_size = 16; in analyse_instr()
3029 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
3032 op->reg = rd + 32; in analyse_instr()
3035 op->type = MKOP(STORE_VSX, PREFIXED, 16); in analyse_instr()
3036 op->element_size = 16; in analyse_instr()
3037 op->vsx_flags = VSX_CHECK_VEC; in analyse_instr()
3041 op->type = MKOP(LOAD, PREFIXED, 16); in analyse_instr()
3044 op->type = MKOP(LOAD, PREFIXED, 8); in analyse_instr()
3048 op->reg = VSX_REGISTER_XTP(rd); in analyse_instr()
3049 op->type = MKOP(LOAD_VSX, PREFIXED, 32); in analyse_instr()
3050 op->element_size = 32; in analyse_instr()
3054 op->type = MKOP(STORE, PREFIXED, 16); in analyse_instr()
3057 op->type = MKOP(STORE, PREFIXED, 8); in analyse_instr()
3061 op->reg = VSX_REGISTER_XTP(rd); in analyse_instr()
3062 op->type = MKOP(STORE_VSX, PREFIXED, 32); in analyse_instr()
3063 op->element_size = 32; in analyse_instr()
3068 case 1: /* Type 01 Eight-Byte Register-to-Register */ in analyse_instr()
3073 op->ea = mlsd_8lsd_ea(word, suffix, regs); in analyse_instr()
3076 op->type = MKOP(LOAD, PREFIXED, 4); in analyse_instr()
3079 op->type = MKOP(LOAD, PREFIXED, 1); in analyse_instr()
3082 op->type = MKOP(STORE, PREFIXED, 4); in analyse_instr()
3085 op->type = MKOP(STORE, PREFIXED, 1); in analyse_instr()
3088 op->type = MKOP(LOAD, PREFIXED, 2); in analyse_instr()
3091 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2); in analyse_instr()
3094 op->type = MKOP(STORE, PREFIXED, 2); in analyse_instr()
3097 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4); in analyse_instr()
3100 op->type = MKOP(LOAD_FP, PREFIXED, 8); in analyse_instr()
3103 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4); in analyse_instr()
3106 op->type = MKOP(STORE_FP, PREFIXED, 8); in analyse_instr()
3110 case 3: /* Type 11 Modified Register-to-Register */ in analyse_instr()
3117 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) { in analyse_instr()
3118 switch (GETTYPE(op->type)) { in analyse_instr()
3132 if ((GETTYPE(op->type) == LOAD_VSX || in analyse_instr()
3133 GETTYPE(op->type) == STORE_VSX) && in analyse_instr()
3135 return -1; in analyse_instr()
3142 op->type = UNKNOWN; in analyse_instr()
3146 if (word & 1) in analyse_instr()
3149 op->reg = ra; in analyse_instr()
3150 op->type |= SETREG; in analyse_instr()
3154 if (word & 1) in analyse_instr()
3157 op->reg = rd; in analyse_instr()
3158 op->type |= SETREG; in analyse_instr()
3162 op->type = INTERRUPT | 0x700; in analyse_instr()
3163 op->val = SRR1_PROGPRIV; in analyse_instr()
3167 op->type = INTERRUPT | 0x700; in analyse_instr()
3168 op->val = SRR1_PROGTRAP; in analyse_instr()
3193 static nokprobe_inline void do_signext(unsigned long *valp, int size) in do_signext() argument
3195 switch (size) { in do_signext()
3205 static nokprobe_inline void do_byterev(unsigned long *valp, int size) in do_byterev() argument
3207 switch (size) { in do_byterev()
3230 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type)); in emulate_update_regs()
3231 switch (GETTYPE(op->type)) { in emulate_update_regs()
3233 if (op->type & SETREG) in emulate_update_regs()
3234 regs->gpr[op->reg] = op->val; in emulate_update_regs()
3235 if (op->type & SETCC) in emulate_update_regs()
3236 regs->ccr = op->ccval; in emulate_update_regs()
3237 if (op->type & SETXER) in emulate_update_regs()
3238 regs->xer = op->xerval; in emulate_update_regs()
3242 if (op->type & SETLK) in emulate_update_regs()
3243 regs->link = next_pc; in emulate_update_regs()
3244 if (op->type & BRTAKEN) in emulate_update_regs()
3245 next_pc = op->val; in emulate_update_regs()
3246 if (op->type & DECCTR) in emulate_update_regs()
3247 --regs->ctr; in emulate_update_regs()
3251 switch (op->type & BARRIER_MASK) { in emulate_update_regs()
3273 switch (op->spr) { in emulate_update_regs()
3275 regs->gpr[op->reg] = regs->xer & 0xffffffffUL; in emulate_update_regs()
3278 regs->gpr[op->reg] = regs->link; in emulate_update_regs()
3281 regs->gpr[op->reg] = regs->ctr; in emulate_update_regs()
3289 switch (op->spr) { in emulate_update_regs()
3291 regs->xer = op->val & 0xffffffffUL; in emulate_update_regs()
3294 regs->link = op->val; in emulate_update_regs()
3297 regs->ctr = op->val; in emulate_update_regs()
3312 * Emulate a previously-analysed load or store instruction.
3315 * -EFAULT = address out of range or access faulted (regs->dar
3317 * -EACCES = misaligned access, instruction requires alignment
3318 * -EINVAL = unknown operation in *op
3322 int err, size, type; in emulate_loadstore() local
3330 size = GETSIZE(op->type); in emulate_loadstore()
3331 type = GETTYPE(op->type); in emulate_loadstore()
3332 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE); in emulate_loadstore()
3333 ea = truncate_if_32bit(regs->msr, op->ea); in emulate_loadstore()
3337 if (ea & (size - 1)) in emulate_loadstore()
3338 return -EACCES; /* can't handle misaligned */ in emulate_loadstore()
3339 if (!address_ok(regs, ea, size)) in emulate_loadstore()
3340 return -EFAULT; in emulate_loadstore()
3343 switch (size) { in emulate_loadstore()
3360 err = do_lqarx(ea, ®s->gpr[op->reg]); in emulate_loadstore()
3364 return -EINVAL; in emulate_loadstore()
3367 regs->dar = ea; in emulate_loadstore()
3370 if (size < 16) in emulate_loadstore()
3371 regs->gpr[op->reg] = val; in emulate_loadstore()
3375 if (ea & (size - 1)) in emulate_loadstore()
3376 return -EACCES; /* can't handle misaligned */ in emulate_loadstore()
3377 if (!address_ok(regs, ea, size)) in emulate_loadstore()
3378 return -EFAULT; in emulate_loadstore()
3380 switch (size) { in emulate_loadstore()
3383 __put_user_asmx(op->val, ea, err, "stbcx.", cr); in emulate_loadstore()
3386 __put_user_asmx(op->val, ea, err, "sthcx.", cr); in emulate_loadstore()
3390 __put_user_asmx(op->val, ea, err, "stwcx.", cr); in emulate_loadstore()
3394 __put_user_asmx(op->val, ea, err, "stdcx.", cr); in emulate_loadstore()
3397 err = do_stqcx(ea, regs->gpr[op->reg], in emulate_loadstore()
3398 regs->gpr[op->reg + 1], &cr); in emulate_loadstore()
3402 return -EINVAL; in emulate_loadstore()
3405 regs->ccr = (regs->ccr & 0x0fffffff) | in emulate_loadstore()
3407 ((regs->xer >> 3) & 0x10000000); in emulate_loadstore()
3409 regs->dar = ea; in emulate_loadstore()
3414 if (size == 16) { in emulate_loadstore()
3415 err = emulate_lq(regs, ea, op->reg, cross_endian); in emulate_loadstore()
3419 err = read_mem(®s->gpr[op->reg], ea, size, regs); in emulate_loadstore()
3421 if (op->type & SIGNEXT) in emulate_loadstore()
3422 do_signext(®s->gpr[op->reg], size); in emulate_loadstore()
3423 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV)) in emulate_loadstore()
3424 do_byterev(®s->gpr[op->reg], size); in emulate_loadstore()
3436 if (!user_mode(regs) && !(regs->msr & MSR_FP)) in emulate_loadstore()
3443 if (!user_mode(regs) && !(regs->msr & MSR_VEC)) in emulate_loadstore()
3445 err = do_vec_load(op->reg, ea, size, regs, cross_endian); in emulate_loadstore()
3456 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) in emulate_loadstore()
3458 if (!user_mode(regs) && !(regs->msr & msrbit)) in emulate_loadstore()
3465 if (!address_ok(regs, ea, size)) in emulate_loadstore()
3466 return -EFAULT; in emulate_loadstore()
3467 rd = op->reg; in emulate_loadstore()
3468 for (i = 0; i < size; i += 4) { in emulate_loadstore()
3471 nb = size - i; in emulate_loadstore()
3479 regs->gpr[rd] = v32; in emulate_loadstore()
3488 if (size == 16) { in emulate_loadstore()
3489 err = emulate_stq(regs, ea, op->reg, cross_endian); in emulate_loadstore()
3493 if ((op->type & UPDATE) && size == sizeof(long) && in emulate_loadstore()
3494 op->reg == 1 && op->update_reg == 1 && !user_mode(regs) && in emulate_loadstore()
3495 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) { in emulate_loadstore()
3500 do_byterev(&op->val, size); in emulate_loadstore()
3501 err = write_mem(op->val, ea, size, regs); in emulate_loadstore()
3506 if (!user_mode(regs) && !(regs->msr & MSR_FP)) in emulate_loadstore()
3513 if (!user_mode(regs) && !(regs->msr & MSR_VEC)) in emulate_loadstore()
3515 err = do_vec_store(op->reg, ea, size, regs, cross_endian); in emulate_loadstore()
3526 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC)) in emulate_loadstore()
3528 if (!user_mode(regs) && !(regs->msr & msrbit)) in emulate_loadstore()
3535 if (!address_ok(regs, ea, size)) in emulate_loadstore()
3536 return -EFAULT; in emulate_loadstore()
3537 rd = op->reg; in emulate_loadstore()
3538 for (i = 0; i < size; i += 4) { in emulate_loadstore()
3539 unsigned int v32 = regs->gpr[rd]; in emulate_loadstore()
3541 nb = size - i; in emulate_loadstore()
3556 return -EINVAL; in emulate_loadstore()
3562 if (op->type & UPDATE) in emulate_loadstore()
3563 regs->gpr[op->update_reg] = op->ea; in emulate_loadstore()
3573 * or -1 if the instruction is one that should not be stepped,
3603 ea = truncate_if_32bit(regs->msr, op.ea); in emulate_step()
3629 regs->dar = ea; in emulate_step()
3635 regs->gpr[op.reg] = regs->msr & MSR_MASK; in emulate_step()
3639 val = regs->gpr[op.reg]; in emulate_step()
3642 return -1; in emulate_step()
3644 regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val)); in emulate_step()
3658 return -1; in emulate_step()
3660 return -1; in emulate_step()
3662 return -1; in emulate_step()
3668 truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type))); in emulate_step()