Lines Matching +full:16 +full:- +full:byte
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
42 .quad 0,-21*8
47 .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
48 .uleb128 9f - 1f; /* length */ \
50 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
51 .byte 0x06; /* DW_OP_deref */ \
52 .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
53 .byte 0x06; /* DW_OP_deref */ \
59 .byte 0x10; /* DW_CFA_expression */ \
61 .uleb128 9f - 1f; /* length */ \
63 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
64 .byte 0x06; /* DW_OP_deref */ \
66 .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
70 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
75 .byte 0x10; /* DW_CFA_expression */ \
77 .uleb128 9f - 1f; /* length */ \
79 .byte 0x30 + regno; /* DW_OP_lit0 */ \
81 .byte 0x40; /* DW_OP_lit16 */ \
82 .byte 0x1e; /* DW_OP_mul */ \
84 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
85 .byte 0x06; /* DW_OP_deref */ \
86 .byte 0x12; /* DW_OP_dup */ \
87 .byte 0x23; /* DW_OP_plus_uconst */ \
89 .byte 0x06; /* DW_OP_deref */ \
90 .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
91 .byte 0x1a; /* DW_OP_and */ \
92 .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
93 .byte 0x30; /* DW_OP_lit0 */ \
94 .byte 0x29; /* DW_OP_eq */ \
95 .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
96 .byte 0x13; /* DW_OP_drop, pop the 0 */ \
97 .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
98 .byte 0x06; /* DW_OP_deref */ \
99 .byte 0x22; /* DW_OP_plus */ \
100 .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
106 .byte 0x10; /* DW_CFA_expression */ \
108 .uleb128 9f - 1f; /* length */ \
110 .byte 0x30 + regno; /* DW_OP_lit n */ \
111 .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
117 .byte 0x10; /* DW_CFA_expression */ \
119 .uleb128 9f - 1f; /* length */ \
121 .byte 0x0a; .short ofs; /* DW_OP_const2u */ \
122 .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
127 .byte 0x10; /* DW_CFA_expression */ \
129 .uleb128 9f - 1f; /* length */ \
131 .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
132 .byte 0x06; /* DW_OP_deref */ \
133 .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
134 .byte 0x06; /* DW_OP_deref */ \
135 .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
151 #define CROFF (RSIZE - CRSIZE)
175 rsave (16, 16*RSIZE); \
220 rsave (48, 48*RSIZE + 16*8); \
256 vsave_msr1 (16); \
272 vsave_msr2 (33, 32*16+12); \
273 vsave (32, 33*16)
280 .long .Lcie_end - .Lcie_start
283 .byte 1 /* Version number */
284 .string "zRS" /* NUL-terminated augmentation string */
286 .sleb128 -8 /* Data alignment factor */
287 .byte 67 /* Return address register column, ap */
289 .byte 0x14 /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
290 .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
294 .long .Lfde0_end - .Lfde0_start
296 .long .Lfde0_start - .Lcie /* CIE pointer. */
297 .quad .Lsigrt_start - . /* PC start, length */
298 .quad .Lsigrt_end - .Lsigrt_start
306 # .byte 0x41 /* DW_CFA_advance_loc 1*4 */