Lines Matching +full:0 +full:- +full:128
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
68 .pvr_mask = 0xffff0000,
69 .pvr_value = 0x00390000,
74 .icache_bsize = 128,
75 .dcache_bsize = 128,
83 .pvr_mask = 0xffff0000,
84 .pvr_value = 0x003c0000,
89 .icache_bsize = 128,
90 .dcache_bsize = 128,
97 { /* PPC970MP DD1.0 - no DEEPNAP, use regular 970 init */
98 .pvr_mask = 0xffffffff,
99 .pvr_value = 0x00440100,
104 .icache_bsize = 128,
105 .dcache_bsize = 128,
113 .pvr_mask = 0xffff0000,
114 .pvr_value = 0x00440000,
119 .icache_bsize = 128,
120 .dcache_bsize = 128,
128 .pvr_mask = 0xffff0000,
129 .pvr_value = 0x00450000,
134 .icache_bsize = 128,
135 .dcache_bsize = 128,
142 .pvr_mask = 0xffff0000,
143 .pvr_value = 0x003a0000,
148 .icache_bsize = 128,
149 .dcache_bsize = 128,
155 .pvr_mask = 0xffffff00,
156 .pvr_value = 0x003b0300,
161 .icache_bsize = 128,
162 .dcache_bsize = 128,
167 .pvr_mask = 0xffff0000,
168 .pvr_value = 0x003b0000,
173 .icache_bsize = 128,
174 .dcache_bsize = 128,
179 { /* POWER6 in P5+ mode; 2.04-compliant processor */
180 .pvr_mask = 0xffffffff,
181 .pvr_value = 0x0f000001,
186 .icache_bsize = 128,
187 .dcache_bsize = 128,
191 .pvr_mask = 0xffff0000,
192 .pvr_value = 0x003e0000,
197 .icache_bsize = 128,
198 .dcache_bsize = 128,
203 { /* 2.05-compliant processor, i.e. Power6 "architected" mode */
204 .pvr_mask = 0xffffffff,
205 .pvr_value = 0x0f000002,
210 .icache_bsize = 128,
211 .dcache_bsize = 128,
214 { /* 2.06-compliant processor, i.e. Power7 "architected" mode */
215 .pvr_mask = 0xffffffff,
216 .pvr_value = 0x0f000003,
222 .icache_bsize = 128,
223 .dcache_bsize = 128,
229 { /* 2.07-compliant processor, i.e. Power8 "architected" mode */
230 .pvr_mask = 0xffffffff,
231 .pvr_value = 0x0f000004,
237 .icache_bsize = 128,
238 .dcache_bsize = 128,
244 { /* 2.07-compliant processor, HeXin C2000 processor */
245 .pvr_mask = 0xffff0000,
246 .pvr_value = 0x00660000,
247 .cpu_name = "HX-C2000",
252 .icache_bsize = 128,
253 .dcache_bsize = 128,
259 { /* 3.00-compliant processor, i.e. Power9 "architected" mode */
260 .pvr_mask = 0xffffffff,
261 .pvr_value = 0x0f000005,
267 .icache_bsize = 128,
268 .dcache_bsize = 128,
273 { /* 3.1-compliant processor, i.e. Power10 "architected" mode */
274 .pvr_mask = 0xffffffff,
275 .pvr_value = 0x0f000006,
281 .icache_bsize = 128,
282 .dcache_bsize = 128,
287 { /* 3.1-compliant processor, i.e. Power11 "architected" mode */
288 .pvr_mask = 0xffffffff,
289 .pvr_value = 0x0f000007,
295 .icache_bsize = 128,
296 .dcache_bsize = 128,
302 .pvr_mask = 0xffff0000,
303 .pvr_value = 0x003f0000,
309 .icache_bsize = 128,
310 .dcache_bsize = 128,
319 .pvr_mask = 0xffff0000,
320 .pvr_value = 0x004A0000,
326 .icache_bsize = 128,
327 .dcache_bsize = 128,
336 .pvr_mask = 0xffff0000,
337 .pvr_value = 0x004b0000,
343 .icache_bsize = 128,
344 .dcache_bsize = 128,
353 .pvr_mask = 0xffff0000,
354 .pvr_value = 0x004c0000,
360 .icache_bsize = 128,
361 .dcache_bsize = 128,
370 .pvr_mask = 0xffff0000,
371 .pvr_value = 0x004d0000,
377 .icache_bsize = 128,
378 .dcache_bsize = 128,
386 { /* Power9 DD2.0 */
387 .pvr_mask = 0xffffefff,
388 .pvr_value = 0x004e0200,
394 .icache_bsize = 128,
395 .dcache_bsize = 128,
404 .pvr_mask = 0xffffefff,
405 .pvr_value = 0x004e0201,
411 .icache_bsize = 128,
412 .dcache_bsize = 128,
421 .pvr_mask = 0xffffefff,
422 .pvr_value = 0x004e0202,
428 .icache_bsize = 128,
429 .dcache_bsize = 128,
438 .pvr_mask = 0xffff0000,
439 .pvr_value = 0x004e0000,
445 .icache_bsize = 128,
446 .dcache_bsize = 128,
455 .pvr_mask = 0xffff0000,
456 .pvr_value = 0x00800000,
462 .icache_bsize = 128,
463 .dcache_bsize = 128,
472 .pvr_mask = 0xffff0000,
473 .pvr_value = 0x00820000,
479 .icache_bsize = 128,
480 .dcache_bsize = 128,
489 .pvr_mask = 0xffff0000,
490 .pvr_value = 0x00700000,
496 .icache_bsize = 128,
497 .dcache_bsize = 128,
500 .platform = "ppc-cell-be",
503 .pvr_mask = 0x7fff0000,
504 .pvr_value = 0x00900000,
518 .pvr_mask = 0x00000000,
519 .pvr_value = 0x00000000,
524 .icache_bsize = 128,
525 .dcache_bsize = 128,