Lines Matching +full:0 +full:x23030
21 #define UNI_N_ADDR_SELECT 0x48
22 #define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
23 #define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
27 #define UNI_N_CFG_GART_BASE 0x8c
28 #define UNI_N_CFG_AGP_BASE 0x90
29 #define UNI_N_CFG_GART_CTRL 0x94
30 #define UNI_N_CFG_INTERNAL_STATUS 0x98
31 #define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
34 #define UNI_N_CFG_GART_INVAL 0x00000001
35 #define UNI_N_CFG_GART_ENABLE 0x00000100
36 #define UNI_N_CFG_GART_2xRESET 0x00010000
37 #define UNI_N_CFG_GART_DISSBADET 0x00020000
39 #define U3_N_CFG_GART_SYNCMODE 0x00040000
40 #define U3_N_CFG_GART_PERFRD 0x00080000
41 #define U3_N_CFG_GART_B2BGNT 0x00200000
42 #define U3_N_CFG_GART_FASTDDR 0x00400000
60 * in the LSB bit (0) that must be set to 1 when the entry is valid.
86 * 0
88 * 0
102 #define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
104 #define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
105 #define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
106 #define UNI_N_VERSION_150 0x0011 /* 1.5 */
107 #define UNI_N_VERSION_200 0x0024 /* 2.0 */
108 #define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
109 #define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
110 #define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
113 #define UNI_N_CLOCK_CNTL 0x0020
114 #define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
115 #define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
116 #define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
117 #define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
120 #define UNI_N_POWER_MGT 0x0030
121 #define UNI_N_POWER_MGT_NORMAL 0x00
122 #define UNI_N_POWER_MGT_IDLE2 0x01
123 #define UNI_N_POWER_MGT_SLEEP 0x02
128 #define UNI_N_ARB_CTRL 0x0040
130 #define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
131 #define UNI_N_ARB_CTRL_QACK_DELAY 0x30
132 #define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
136 * on this register being 0 or not
138 #define UNI_N_CPU_NUMBER 0x0050
143 #define UNI_N_HWINIT_STATE 0x0070
144 #define UNI_N_HWINIT_STATE_SLEEPING 0x01
145 #define UNI_N_HWINIT_STATE_RUNNING 0x02
147 * CPU has started and will enter its sleep loop with IP=0
149 #define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
154 #define UNI_N_AACK_DELAY 0x0100
155 #define UNI_N_AACK_DELAY_ENABLE 0x00000001
158 #define UNI_N_CLOCK_STOP_STATUS0 0x0150
159 #define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
160 #define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
161 #define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
162 #define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
163 #define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
164 #define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
165 #define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
166 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
167 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
168 #define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
169 #define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
170 #define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
171 #define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
172 #define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
173 #define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
174 #define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
175 #define UNI_N_CLOCK_STOPPED_USB0 0x00000020
176 #define UNI_N_CLOCK_STOPPED_USB1 0x00000010
177 #define UNI_N_CLOCK_STOPPED_USB2 0x00000008
178 #define UNI_N_CLOCK_STOPPED_32 0x00000004
179 #define UNI_N_CLOCK_STOPPED_45 0x00000002
180 #define UNI_N_CLOCK_STOPPED_49 0x00000001
182 #define UNI_N_CLOCK_STOP_STATUS1 0x0160
183 #define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
184 #define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
185 #define UNI_N_CLOCK_STOPPED_CPU 0x00020000
186 #define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
187 #define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
188 #define UNI_N_CLOCK_STOPPED_FW 0x00004000
189 #define UNI_N_CLOCK_STOPPED_GB 0x00002000
190 #define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
191 #define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
192 #define UNI_N_CLOCK_STOPPED_MAX 0x00000400
193 #define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
194 #define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
195 #define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
196 #define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
197 #define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
198 #define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
199 #define UNI_N_CLOCK_STOPPED_AGP 0x00000004
200 #define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
201 #define UNI_N_CLOCK_STOPPED_18 0x00000001
204 #define UNI_N_CLOCK_SPREADING 0x190
206 /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
215 #define U3_TOGGLE_REG 0x00e0
216 #define U3_PMC_START_STOP 0x0001
217 #define U3_MPIC_RESET 0x0002
218 #define U3_MPIC_OUTPUT_ENABLE 0x0004
221 #define U3_API_PHY_CONFIG_1 0x23030
224 #define U3_HT_CONFIG_BASE 0x70000
225 #define U3_HT_LINK_COMMAND 0x100
226 #define U3_HT_LINK_CONFIG 0x110
227 #define U3_HT_LINK_FREQ 0x120