Lines Matching +full:general +full:- +full:purpose
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
47 /* Special Purpose Registers (SPRNs)*/
50 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
51 #define SPRN_SPRG3R 0x103 /* Special Purpose Register General 3 Read */
52 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
53 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
54 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
55 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
56 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
57 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
58 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
59 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
136 #define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
137 #define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161 #define SPRN_SLER 0x3BB /* Little-endian real mode */
197 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
214 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
216 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
226 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
229 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
230 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
241 #define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
243 #define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
267 #define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
294 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
295 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
296 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
297 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
298 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
299 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
300 #define ESR_PPR 0x04000000 /* Program Exception - Privileged */
301 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
303 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
304 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
341 #define dbcr_dac(task) ((task)->thread.debug.dbcr0)
358 #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
359 #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
360 #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
371 #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
372 #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
373 #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
375 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
378 #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
381 #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
388 #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
389 #define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
390 #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
391 #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
392 #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
463 #define DCWR_COPY 0 /* Copy-back */
464 #define DCWR_WRITE 1 /* Write-through */