Lines Matching +full:disable +full:- +full:mmu +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright 2009-2010 Freescale Semiconductor, Inc.
12 #include <asm/ppc-opcode.h>
16 #define MSR_UCLE_LG 26 /* User-mode cache lock enable */
23 #define MSR_CM_LG 31 /* Computation Mode (0=32-bit, 1=64-bit) */
69 #define SPRN_MAS8 0x155 /* MMU Assist Register 8 */
72 #define SPRN_MAS5_MAS6 0x15c /* MMU Assist Register 5 || 6 */
73 #define SPRN_MAS8_MAS1 0x15d /* MMU Assist Register 8 || 1 */
79 #define SPRN_MAS7_MAS3 0x174 /* MMU Assist Register 7 || 3 */
80 #define SPRN_MAS0_MAS1 0x175 /* MMU Assist Register 0 || 1 */
139 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
140 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
141 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
142 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
143 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
144 #define SPRN_MAS5 0x153 /* MMU Assist Register 5 */
145 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
154 #define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
155 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */
160 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
161 #define SPRN_SLER 0x3BB /* Little-endian real mode */
167 #define SPRN_MMUCSR0 0x3F4 /* MMU Control and Status Register 0 */
168 #define SPRN_MMUCFG 0x3F7 /* MMU Configuration Register */
197 #define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
214 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
215 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
216 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
226 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
229 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
230 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
241 #define MCSR_DCPERR_MC 0x20000000UL /* D-Cache Parity Error */
243 #define MCSR_NMI 0x00100000UL /* Non-Maskable Interrupt */
267 #define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
274 #define DBSR_MRR 0x30000000 /* Most Recent Reset */
294 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
295 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
296 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
297 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
298 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
299 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
300 #define ESR_PPR 0x04000000 /* Program Exception - Privileged */
301 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
303 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
304 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
317 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
318 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
319 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */
320 #define DBCR0_RST_NONE 0x00000000 /* No Reset */
341 #define dbcr_dac(task) ((task)->thread.debug.dbcr0)
358 #define DBCR1_IAC12M 0x00800000 /* Instr Addr 1-2 range enable */
359 #define DBCR1_IAC12MX 0x00C00000 /* Instr Addr 1-2 range eXclusive */
360 #define DBCR1_IAC12AT 0x00010000 /* Instr Addr 1-2 range Toggle */
371 #define DBCR1_IAC34M 0x00000080 /* Instr Addr 3-4 range enable */
372 #define DBCR1_IAC34MX 0x000000C0 /* Instr Addr 3-4 range eXclusive */
373 #define DBCR1_IAC34AT 0x00000001 /* Instr Addr 3-4 range Toggle */
375 #define dbcr_iac_range(task) ((task)->thread.debug.dbcr1)
378 #define DBCR_IAC12MODE DBCR1_IAC12MX /* IAC 1-2 Mode Bits */
381 #define DBCR_IAC34MODE DBCR1_IAC34MX /* IAC 3-4 Mode Bits */
388 #define DBCR2_DAC12M 0x00800000 /* DAC 1-2 range enable */
389 #define DBCR2_DAC12MM 0x00400000 /* DAC 1-2 Mask mode*/
390 #define DBCR2_DAC12MX 0x00C00000 /* DAC 1-2 range eXclusive */
391 #define DBCR2_DAC12MODE 0x00C00000 /* DAC 1-2 Mode Bits */
392 #define DBCR2_DAC12A 0x00200000 /* DAC 1-2 Asynchronous */
421 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
423 #define WRC_NONE 0 /* No reset will occur */
424 #define WRC_CORE 1 /* Core reset will occur */
425 #define WRC_CHIP 2 /* Chip reset will occur */
426 #define WRC_SYSTEM 3 /* System reset will occur */
449 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
450 #define WRS_NONE 0 /* No WDT reset occurred */
451 #define WRS_CORE 1 /* WDT forced core reset */
452 #define WRS_CHIP 2 /* WDT forced chip reset */
453 #define WRS_SYSTEM 3 /* WDT forced system reset */
463 #define DCWR_COPY 0 /* Copy-back */
464 #define DCWR_WRITE 1 /* Write-through */
480 #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
523 #define SPRN_EPCR_DUVD 0x04000000 /* Disable Hypervisor Debug */
527 #define SPRN_EPCR_DGTMI 0x00800000 /* Disable TLB Guest Management
529 #define SPRN_EPCR_DMIUH 0x00400000 /* Disable MAS Interrupt updates