Lines Matching +full:everything +full:- +full:else

1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <asm-generic/pgtable-nopmd.h>
10 #include <asm/mmu.h>			/* For sub-arch specific PPC_PIN_SIZE */
17 #define PGD_INDEX_SIZE	(32 - PGDIR_SHIFT)
28 #define PMD_MASKED_BITS (PTE_TABLE_SIZE - 1)
35  * The normal case is that PTEs are 32-bits and we have a 1-page
36  * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
38  * For any >32-bit physical address platform, we can use the following
41  * level has 2048 entries and the second level has 512 64-bit PTE entries.
42  * -Matt
44 /* PGDIR_SHIFT determines what a top-level page table entry can map */
47 #define PGDIR_MASK	(~(PGDIR_SIZE-1))
66 #define FIXADDR_TOP	(KASAN_SHADOW_START - PAGE_SIZE)
67 #else
68 #define FIXADDR_TOP	((unsigned long)(-PAGE_SIZE))
78 #else
90  * any out-of-bounds memory accesses will hopefully be caught.
101  * of RAM.  -- Cort
105 …e VMALLOC_START (((ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
106 #else
107 #define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
112 #else
117  * Bits in a linux-style PTE.  These match the bits in the
118  * (hardware-defined) PowerPC PTE as closely as possible.
122 #include <asm/nohash/32/pte-44x.h>
124 #include <asm/nohash/pte-e500.h>
126 #include <asm/nohash/32/pte-85xx.h>
128 #include <asm/nohash/32/pte-8xx.h>
132  * Location of the PFN in the PTE. Most 32-bit platforms use the same
134  * Platform who don't just pre-define the value so we don't override it here.
141  * The mask covered by the RPN must be a ULL on 32-bit platforms with
142  * 64-bit PTEs.
145 #define PTE_RPN_MASK	(~((1ULL << PTE_RPN_SHIFT) - 1))
147 #else
148 #define PTE_RPN_MASK	(~((1UL << PTE_RPN_SHIFT) - 1))
165  * because everything runs with translation enabled (even the TLB miss
166  * handler).  On everything else the pmd contains the physical address
167  * of the pte page.  -- paulus
171 #else
173 	((const void *)((unsigned long)pmd_val(pmd) & ~(PTE_TABLE_SIZE - 1)))
187  *   <------------------ offset -------------------> < type -> E 0 0