Lines Matching +full:0 +full:x0000000080000000
21 PPC_PMC_DEFAULT = 0,
77 * if the error is fatal, 1 if it was fully recovered and 0 to
111 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
112 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
113 #define CPU_FTR_DBELL ASM_CONST(0x00000004)
114 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
115 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
116 // ASM_CONST(0x00000020) Free
117 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
118 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
119 #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
120 #define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
124 #define CPU_FTR_L2CR ASM_CONST(0x00002000)
125 #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
126 #define CPU_FTR_TAU ASM_CONST(0x00008000)
127 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
128 #define CPU_FTR_L3CR ASM_CONST(0x00040000)
129 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
130 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
131 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
132 #define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
133 #define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
134 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
135 #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
136 #define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
137 #define CPU_FTR_SPE ASM_CONST(0x10000000)
138 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
139 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
142 /* Define these to 0 for the sake of tests in common code */
143 #define CPU_FTR_PPC_LE (0)
144 #define CPU_FTR_SPE (0)
149 * on 32-bit, make the names available but defined to be 0.
154 #define LONG_ASM_CONST(x) 0
157 #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
158 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
159 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
160 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
161 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
162 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
163 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
164 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
165 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
166 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
167 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
168 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
169 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
170 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
171 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
172 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
173 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
174 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
175 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
176 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
177 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
178 /* LONG_ASM_CONST(0x0000000400000000) Free */
179 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
180 #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
181 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
182 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
183 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
184 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
185 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
186 #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
187 #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
188 #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
189 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
190 #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
191 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
192 #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
193 #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
194 #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
195 #define CPU_FTR_DEXCR_NPHIE LONG_ASM_CONST(0x0010000000000000)
196 #define CPU_FTR_P11_PVR LONG_ASM_CONST(0x0020000000000000)
209 #define CPU_FTR_ALTIVEC_COMP 0
210 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
220 #define CPU_FTR_VSX_COMP 0
221 #define PPC_FEATURE_HAS_VSX_COMP 0
233 #define CPU_FTR_SPE_COMP 0
234 #define PPC_FEATURE_HAS_SPE_COMP 0
235 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
236 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
245 #define CPU_FTR_TM_COMP 0
246 #define PPC_FEATURE2_HTM_COMP 0
247 #define PPC_FEATURE2_HTM_NOSC_COMP 0
260 #define CPU_FTR_COMMON 0
270 #define CPU_FTR_MAYBE_CAN_DOZE 0
271 #define CPU_FTR_MAYBE_CAN_NAP 0
521 0,
542 #define CPU_FTRS_DT_CPU_BASE (~0ul)