Lines Matching +full:0 +full:x00007000
29 char res2[0xc];
31 char res3[0x4c];
53 char res1[0x20];
83 char res1[0x24];
92 char res3[0x80];
98 #define BR_BA_MSK 0xffff8000 /* Base Address Mask */
99 #define BR_AT_MSK 0x00007000 /* Address Type Mask */
100 #define BR_PS_MSK 0x00000c00 /* Port Size Mask */
101 #define BR_PS_32 0x00000000 /* 32 bit port size */
102 #define BR_PS_16 0x00000800 /* 16 bit port size */
103 #define BR_PS_8 0x00000400 /* 8 bit port size */
104 #define BR_PARE 0x00000200 /* Parity Enable */
105 #define BR_WP 0x00000100 /* Write Protect */
106 #define BR_MS_MSK 0x000000c0 /* Machine Select Mask */
107 #define BR_MS_GPCM 0x00000000 /* G.P.C.M. Machine Select */
108 #define BR_MS_UPMA 0x00000080 /* U.P.M.A Machine Select */
109 #define BR_MS_UPMB 0x000000c0 /* U.P.M.B Machine Select */
110 #define BR_V 0x00000001 /* Bank Valid */
115 #define OR_AM_MSK 0xffff8000 /* Address Mask Mask */
116 #define OR_ATM_MSK 0x00007000 /* Address Type Mask Mask */
117 #define OR_CSNT_SAM 0x00000800 /* Chip Select Negation Time/ Start */
119 #define OR_ACS_MSK 0x00000600 /* Address to Chip Select Setup mask */
120 #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121 #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122 #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
123 #define OR_G5LA 0x00000400 /* Output #GPL5 on #GPL_A5 */
124 #define OR_G5LS 0x00000200 /* Drive #GPL high on falling edge of...*/
125 #define OR_BI 0x00000100 /* Burst inhibit */
126 #define OR_SCY_MSK 0x000000f0 /* Cycle Length in Clocks */
127 #define OR_SCY_0_CLK 0x00000000 /* 0 clock cycles wait states */
128 #define OR_SCY_1_CLK 0x00000010 /* 1 clock cycles wait states */
129 #define OR_SCY_2_CLK 0x00000020 /* 2 clock cycles wait states */
130 #define OR_SCY_3_CLK 0x00000030 /* 3 clock cycles wait states */
131 #define OR_SCY_4_CLK 0x00000040 /* 4 clock cycles wait states */
132 #define OR_SCY_5_CLK 0x00000050 /* 5 clock cycles wait states */
133 #define OR_SCY_6_CLK 0x00000060 /* 6 clock cycles wait states */
134 #define OR_SCY_7_CLK 0x00000070 /* 7 clock cycles wait states */
135 #define OR_SCY_8_CLK 0x00000080 /* 8 clock cycles wait states */
136 #define OR_SCY_9_CLK 0x00000090 /* 9 clock cycles wait states */
137 #define OR_SCY_10_CLK 0x000000a0 /* 10 clock cycles wait states */
138 #define OR_SCY_11_CLK 0x000000b0 /* 11 clock cycles wait states */
139 #define OR_SCY_12_CLK 0x000000c0 /* 12 clock cycles wait states */
140 #define OR_SCY_13_CLK 0x000000d0 /* 13 clock cycles wait states */
141 #define OR_SCY_14_CLK 0x000000e0 /* 14 clock cycles wait states */
142 #define OR_SCY_15_CLK 0x000000f0 /* 15 clock cycles wait states */
143 #define OR_SETA 0x00000008 /* External Transfer Acknowledge */
144 #define OR_TRLX 0x00000004 /* Timing Relaxed */
145 #define OR_EHTR 0x00000002 /* Extended Hold Time on Read */
151 char res0[0x02];
154 char res1[0x14];
156 char res2[0x02];
160 char res3[0x10];
165 char res5[0x34];
168 #define TBSCR_TBIRQ_MASK ((ushort)0xff00)
169 #define TBSCR_REFA ((ushort)0x0080)
170 #define TBSCR_REFB ((ushort)0x0040)
171 #define TBSCR_REFAE ((ushort)0x0008)
172 #define TBSCR_REFBE ((ushort)0x0004)
173 #define TBSCR_TBF ((ushort)0x0002)
174 #define TBSCR_TBE ((ushort)0x0001)
176 #define RTCSC_RTCIRQ_MASK ((ushort)0xff00)
177 #define RTCSC_SEC ((ushort)0x0080)
178 #define RTCSC_ALR ((ushort)0x0040)
179 #define RTCSC_38K ((ushort)0x0010)
180 #define RTCSC_SIE ((ushort)0x0008)
181 #define RTCSC_ALE ((ushort)0x0004)
182 #define RTCSC_RTF ((ushort)0x0002)
183 #define RTCSC_RTE ((ushort)0x0001)
185 #define PISCR_PIRQ_MASK ((ushort)0xff00)
186 #define PISCR_PS ((ushort)0x0080)
187 #define PISCR_PIE ((ushort)0x0004)
188 #define PISCR_PTF ((ushort)0x0002)
189 #define PISCR_PTE ((ushort)0x0001)
197 char res[0x74]; /* Reserved area */
207 char res1[0x10];
212 char res2[0x10];
215 char res3[0x38];
224 char res[0x474];
229 #define KAPWR_KEY ((unsigned int)0x55ccaa33)
248 u_char res5[0x18];
261 char res2[0x7];
278 char res6[0x8b];
297 char res8[0x13];
304 char res[0xe];
337 char res1[0xe];
423 uint res9[0x1e]; /* reserved */
431 u_char fl_un_cmap[0x200];
451 u_char res6[0x14];
514 u_char res17[0xc];
518 u_char cp_vcram[0x100];
519 u_char cp_siram[0x200];
528 char res18[0xE00];
539 u_char cp_dpmem[0x1C00]; /* BD / Data / ucode */
540 u_char cp_dparam[0x400]; /* Parameter RAM */