Lines Matching +full:0 +full:- +full:32
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
5 # Copyright 2023- IBM Corp. All rights reserved
43 #include <asm/asm-offsets.h>
44 #include <asm/asm-compat.h>
79 mflr 0
80 std 0, 16(1)
81 stdu 1,-752(1)
103 SAVE_VRS 20, 0, 9
105 SAVE_VRS 22, 32, 9
138 RESTORE_VRS 20, 0, 9
140 RESTORE_VRS 22, 32, 9
190 ld 0, 16(1)
191 mtlr 0
196 xxlor 0, 32+25, 32+25
197 xxlor 32+25, 20, 20
198 vadduwm 0, 0, 4
207 vpermxor 12, 12, 0, 25
215 xxlor 32+25, 0, 0
233 xxlor 0, 32+25, 32+25
234 xxlor 32+25, 21, 21
243 xxlor 32+25, 0, 0
244 vadduwm 0, 0, 4
253 xxlor 0, 32+25, 32+25
254 xxlor 32+25, 22, 22
255 vpermxor 12, 12, 0, 25
263 xxlor 32+25, 0, 0
272 xxlor 0, 32+28, 32+28
273 xxlor 32+28, 23, 23
290 xxlor 32+28, 0, 0
293 xxlor 0, 32+25, 32+25
294 xxlor 32+25, 20, 20
295 vadduwm 0, 0, 5
304 vpermxor 15, 15, 0, 25
313 xxlor 32+25, 0, 0
331 xxlor 0, 32+25, 32+25
332 xxlor 32+25, 21, 21
341 xxlor 32+25, 0, 0
343 vadduwm 0, 0, 5
352 xxlor 0, 32+25, 32+25
353 xxlor 32+25, 22, 22
354 vpermxor 15, 15, 0, 25
362 xxlor 32+25, 0, 0
373 xxlor 0, 32+28, 32+28
374 xxlor 32+28, 23, 23
391 xxlor 32+28, 0, 0
396 vadduwm 0, 0, 4
400 vpermxor 12, 12, 0, 20
416 vadduwm 0, 0, 4
420 vpermxor 12, 12, 0, 22
438 vadduwm 0, 0, 5
442 vpermxor 15, 15, 0, 20
458 vadduwm 0, 0, 5
462 vpermxor 15, 15, 0, 22
482 xxmrghw 10, 32+\a0, 32+\a1 # a0, a1, b0, b1
483 xxmrghw 11, 32+\a2, 32+\a3 # a2, a3, b2, b3
484 xxmrglw 12, 32+\a0, 32+\a1 # c0, c1, d0, d1
485 xxmrglw 13, 32+\a2, 32+\a3 # c2, c3, d2, d3
486 xxpermdi 32+\a0, 10, 11, 0 # a0, a1, a2, a3
487 xxpermdi 32+\a1, 10, 11, 3 # b0, b1, b2, b3
488 xxpermdi 32+\a2, 12, 13, 0 # c0, c1, c2, c3
489 xxpermdi 32+\a3, 12, 13, 3 # d0, d1, d2, d3
494 vadduwm \S+0, \S+0, 16-\S
495 vadduwm \S+4, \S+4, 17-\S
496 vadduwm \S+8, \S+8, 18-\S
497 vadduwm \S+12, \S+12, 19-\S
499 vadduwm \S+1, \S+1, 16-\S
500 vadduwm \S+5, \S+5, 17-\S
501 vadduwm \S+9, \S+9, 18-\S
502 vadduwm \S+13, \S+13, 19-\S
504 vadduwm \S+2, \S+2, 16-\S
505 vadduwm \S+6, \S+6, 17-\S
506 vadduwm \S+10, \S+10, 18-\S
507 vadduwm \S+14, \S+14, 19-\S
509 vadduwm \S+3, \S+3, 16-\S
510 vadduwm \S+7, \S+7, 17-\S
511 vadduwm \S+11, \S+11, 18-\S
512 vadduwm \S+15, \S+15, 19-\S
521 lxvw4x 0, 0, 9
538 xxlxor \S+32, \S+32, 0
555 stxvw4x \S+32, 0, 16
582 cmpdi 6, 0
587 # r17 - r31 mainly for Write_256 macro.
589 li 18, 32
605 li 14, 0 # offset to inp and outp
607 lxvw4x 48, 0, 3 # vr16, constants
612 # create (0, 1, 2, 3) counters
613 vspltisw 0, 0
617 vmrghw 4, 0, 1
619 vsldoi 30, 4, 5, 8 # vr30 counter, 4 (0, 1, 2, 3)
626 lxvw4x 32+20, 0, 11
627 lxvw4x 32+22, 17, 11
642 xxlor 25, 32+26, 32+26
643 xxlor 24, 32+25, 32+25
645 vadduwm 31, 30, 25 # counter = (0, 1, 2, 3) + (4, 4, 4, 4)
646 xxlor 30, 32+30, 32+30
647 xxlor 31, 32+31, 32+31
649 xxlor 20, 32+20, 32+20
650 xxlor 21, 32+21, 32+21
651 xxlor 22, 32+22, 32+22
652 xxlor 23, 32+23, 32+23
658 xxspltw 32+0, 16, 0
659 xxspltw 32+1, 16, 1
660 xxspltw 32+2, 16, 2
661 xxspltw 32+3, 16, 3
663 xxspltw 32+4, 17, 0
664 xxspltw 32+5, 17, 1
665 xxspltw 32+6, 17, 2
666 xxspltw 32+7, 17, 3
667 xxspltw 32+8, 18, 0
668 xxspltw 32+9, 18, 1
669 xxspltw 32+10, 18, 2
670 xxspltw 32+11, 18, 3
671 xxspltw 32+12, 19, 0
672 xxspltw 32+13, 19, 1
673 xxspltw 32+14, 19, 2
674 xxspltw 32+15, 19, 3
677 xxspltw 32+16, 16, 0
678 xxspltw 32+17, 16, 1
679 xxspltw 32+18, 16, 2
680 xxspltw 32+19, 16, 3
682 xxspltw 32+20, 17, 0
683 xxspltw 32+21, 17, 1
684 xxspltw 32+22, 17, 2
685 xxspltw 32+23, 17, 3
686 xxspltw 32+24, 18, 0
687 xxspltw 32+25, 18, 1
688 xxspltw 32+26, 18, 2
689 xxspltw 32+27, 18, 3
690 xxspltw 32+28, 19, 0
691 xxspltw 32+29, 19, 1
693 xxspltw 32+30, 19, 2
694 xxspltw 32+31, 19, 3
702 xxlor 0, 32+30, 32+30
703 xxlor 32+30, 30, 30
705 xxlor 32+30, 0, 0
706 TP_4x 0, 1, 2, 3
711 xxlor 0, 48, 48
719 Add_state 0
720 xxlor 48, 0, 0
724 Write_256 0
726 addi 15, 15, -256 # len -=256
728 xxlor 5, 32+31, 32+31
729 xxlor 32+31, 31, 31
731 xxlor 32+31, 5, 5
732 TP_4x 16+0, 16+1, 16+2, 16+3
737 xxlor 32, 16, 16
744 addi 15, 15, -256 # len +=256
746 xxlor 32+24, 24, 24
747 xxlor 32+25, 25, 25
748 xxlor 32+30, 30, 30
751 xxlor 30, 32+30, 32+30
752 xxlor 31, 32+31, 32+31
754 cmpdi 15, 0
764 lxvw4x 48, 0, 3 # vr16, constants
773 lxvw4x 32+20, 0, 11
774 lxvw4x 32+22, 17, 11
780 vspltw 0, 16, 0
785 vspltw 4, 17, 0
789 vspltw 8, 18, 0
793 vspltw 12, 19, 0
806 TP_4x 0, 1, 2, 3
811 Add_state 0
812 Write_256 0
814 addi 15, 15, -256 # len += 256
820 cmpdi 15, 0
833 li 3, 0
840 .long 0x22330011, 0x66774455, 0xaabb8899, 0xeeffccdd
841 .long 0x11223300, 0x55667744, 0x99aabb88, 0xddeeffcc