Lines Matching +full:secondary +full:- +full:boot +full:- +full:reg
1 // SPDX-License-Identifier: GPL-2.0-only
6 * XPedite5370 3U VPX single-board computer based on MPC8572E
9 /dts-v1/;
13 #address-cells = <2>;
14 #size-cells = <2>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 reg = <0x0>;
32 d-cache-line-size = <32>; // 32 bytes
33 i-cache-line-size = <32>; // 32 bytes
34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
36 timebase-frequency = <0>;
37 bus-frequency = <0>;
38 clock-frequency = <0>;
39 next-level-cache = <&L2>;
44 reg = <0x1>;
45 d-cache-line-size = <32>; // 32 bytes
46 i-cache-line-size = <32>; // 32 bytes
47 d-cache-size = <0x8000>; // L1, 32K
48 i-cache-size = <0x8000>; // L1, 32K
49 timebase-frequency = <0>;
50 bus-frequency = <0>;
51 clock-frequency = <0>;
52 next-level-cache = <&L2>;
58 reg = <0x0 0x0 0x0 0x0>; // Filled in by U-Boot
62 #address-cells = <2>;
63 #size-cells = <1>;
64 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
65 reg = <0 0xef005000 0 0x1000>;
67 interrupt-parent = <&mpic>;
69 ranges = <0 0 0 0xf8000000 0x8000000 /* CS0: Boot flash */
74 nor-boot@0,0 {
75 compatible = "amd,s29gl01gp", "cfi-flash";
76 bank-width = <2>;
77 reg = <0 0 0x8000000>; /* 128MB */
78 #address-cells = <1>;
79 #size-cells = <1>;
82 reg = <0x00000000 0x6f00000>; /* 111 MB */
86 reg = <0x6f00000 0x1000000>; /* 16 MB */
90 reg = <0x7f00000 0x40000>; /* 256 KB */
93 label = "Primary U-Boot environment";
94 reg = <0x7f40000 0x40000>; /* 256 KB */
97 label = "Primary U-Boot";
98 reg = <0x7f80000 0x80000>; /* 512 KB */
99 read-only;
103 nor-alternate@1,0 {
104 compatible = "amd,s29gl01gp", "cfi-flash";
105 bank-width = <2>;
106 //reg = <0xf0000000 0x08000000>; /* 128MB */
107 reg = <1 0 0x8000000>; /* 128MB */
108 #address-cells = <1>;
109 #size-cells = <1>;
111 label = "Secondary user space";
112 reg = <0x00000000 0x6f00000>; /* 111 MB */
115 label = "Secondary kernel";
116 reg = <0x6f00000 0x1000000>; /* 16 MB */
119 label = "Secondary DTB";
120 reg = <0x7f00000 0x40000>; /* 256 KB */
123 label = "Secondary U-Boot environment";
124 reg = <0x7f40000 0x40000>; /* 256 KB */
127 label = "Secondary U-Boot";
128 reg = <0x7f80000 0x80000>; /* 512 KB */
129 read-only;
134 #address-cells = <1>;
135 #size-cells = <1>;
142 compatible = "fsl,mpc8572-fcm-nand",
143 "fsl,elbc-fcm-nand";
144 reg = <2 0 0x40000>;
145 /* U-Boot should fix this up if chip size > 1 GB */
148 reg = <0 0x40000000>;
155 #address-cells = <1>;
156 #size-cells = <1>;
158 compatible = "fsl,mpc8572-immr", "simple-bus";
160 bus-frequency = <0>; // Filled out by uboot.
162 ecm-law@0 {
163 compatible = "fsl,ecm-law";
164 reg = <0x0 0x1000>;
165 fsl,num-laws = <12>;
169 compatible = "fsl,mpc8572-ecm", "fsl,ecm";
170 reg = <0x1000 0x1000>;
172 interrupt-parent = <&mpic>;
175 memory-controller@2000 {
176 compatible = "fsl,mpc8572-memory-controller";
177 reg = <0x2000 0x1000>;
178 interrupt-parent = <&mpic>;
182 memory-controller@6000 {
183 compatible = "fsl,mpc8572-memory-controller";
184 reg = <0x6000 0x1000>;
185 interrupt-parent = <&mpic>;
189 L2: l2-cache-controller@20000 {
190 compatible = "fsl,mpc8572-l2-cache-controller";
191 reg = <0x20000 0x1000>;
192 cache-line-size = <32>; // 32 bytes
193 cache-size = <0x100000>; // L2, 1M
194 interrupt-parent = <&mpic>;
199 #address-cells = <1>;
200 #size-cells = <0>;
201 cell-index = <0>;
202 compatible = "fsl-i2c";
203 reg = <0x3000 0x100>;
205 interrupt-parent = <&mpic>;
208 temp-sensor@48 {
210 reg = <0x48>;
213 temp-sensor@4c {
215 reg = <0x4c>;
218 cpu-supervisor@51 {
220 reg = <0x51>;
225 reg = <0x54>;
231 reg = <0x68>;
234 pcie-switch@70 {
236 reg = <0x70>;
241 reg = <0x18>;
242 #gpio-cells = <2>;
243 gpio-controller;
249 reg = <0x1c>;
250 #gpio-cells = <2>;
251 gpio-controller;
257 reg = <0x1e>;
258 #gpio-cells = <2>;
259 gpio-controller;
265 reg = <0x1f>;
266 #gpio-cells = <2>;
267 gpio-controller;
273 #address-cells = <1>;
274 #size-cells = <0>;
275 cell-index = <1>;
276 compatible = "fsl-i2c";
277 reg = <0x3100 0x100>;
279 interrupt-parent = <&mpic>;
284 #address-cells = <1>;
285 #size-cells = <1>;
286 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
287 reg = <0xc300 0x4>;
289 cell-index = <1>;
290 dma-channel@0 {
291 compatible = "fsl,mpc8572-dma-channel",
292 "fsl,eloplus-dma-channel";
293 reg = <0x0 0x80>;
294 cell-index = <0>;
295 interrupt-parent = <&mpic>;
298 dma-channel@80 {
299 compatible = "fsl,mpc8572-dma-channel",
300 "fsl,eloplus-dma-channel";
301 reg = <0x80 0x80>;
302 cell-index = <1>;
303 interrupt-parent = <&mpic>;
306 dma-channel@100 {
307 compatible = "fsl,mpc8572-dma-channel",
308 "fsl,eloplus-dma-channel";
309 reg = <0x100 0x80>;
310 cell-index = <2>;
311 interrupt-parent = <&mpic>;
314 dma-channel@180 {
315 compatible = "fsl,mpc8572-dma-channel",
316 "fsl,eloplus-dma-channel";
317 reg = <0x180 0x80>;
318 cell-index = <3>;
319 interrupt-parent = <&mpic>;
325 #address-cells = <1>;
326 #size-cells = <1>;
327 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
328 reg = <0x21300 0x4>;
330 cell-index = <0>;
331 dma-channel@0 {
332 compatible = "fsl,mpc8572-dma-channel",
333 "fsl,eloplus-dma-channel";
334 reg = <0x0 0x80>;
335 cell-index = <0>;
336 interrupt-parent = <&mpic>;
339 dma-channel@80 {
340 compatible = "fsl,mpc8572-dma-channel",
341 "fsl,eloplus-dma-channel";
342 reg = <0x80 0x80>;
343 cell-index = <1>;
344 interrupt-parent = <&mpic>;
347 dma-channel@100 {
348 compatible = "fsl,mpc8572-dma-channel",
349 "fsl,eloplus-dma-channel";
350 reg = <0x100 0x80>;
351 cell-index = <2>;
352 interrupt-parent = <&mpic>;
355 dma-channel@180 {
356 compatible = "fsl,mpc8572-dma-channel",
357 "fsl,eloplus-dma-channel";
358 reg = <0x180 0x80>;
359 cell-index = <3>;
360 interrupt-parent = <&mpic>;
367 #address-cells = <1>;
368 #size-cells = <1>;
369 cell-index = <0>;
373 reg = <0x24000 0x1000>;
375 local-mac-address = [ 00 00 00 00 00 00 ];
377 interrupt-parent = <&mpic>;
378 tbi-handle = <&tbi0>;
379 phy-handle = <&phy0>;
380 phy-connection-type = "sgmii";
383 #address-cells = <1>;
384 #size-cells = <0>;
385 compatible = "fsl,gianfar-mdio";
386 reg = <0x520 0x20>;
388 phy0: ethernet-phy@1 {
389 interrupt-parent = <&mpic>;
391 reg = <0x1>;
393 phy1: ethernet-phy@2 {
394 interrupt-parent = <&mpic>;
396 reg = <0x2>;
398 tbi0: tbi-phy@11 {
399 reg = <0x11>;
400 device_type = "tbi-phy";
407 #address-cells = <1>;
408 #size-cells = <1>;
409 cell-index = <1>;
413 reg = <0x25000 0x1000>;
415 local-mac-address = [ 00 00 00 00 00 00 ];
417 interrupt-parent = <&mpic>;
418 tbi-handle = <&tbi1>;
419 phy-handle = <&phy1>;
420 phy-connection-type = "sgmii";
423 #address-cells = <1>;
424 #size-cells = <0>;
425 compatible = "fsl,gianfar-tbi";
426 reg = <0x520 0x20>;
428 tbi1: tbi-phy@11 {
429 reg = <0x11>;
430 device_type = "tbi-phy";
437 cell-index = <0>;
440 reg = <0x4500 0x100>;
441 clock-frequency = <0>;
443 interrupt-parent = <&mpic>;
448 cell-index = <1>;
451 reg = <0x4600 0x100>;
452 clock-frequency = <0>;
454 interrupt-parent = <&mpic>;
457 global-utilities@e0000 { //global utilities block
458 compatible = "fsl,mpc8572-guts";
459 reg = <0xe0000 0x1000>;
460 fsl,has-rstcr;
464 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
465 reg = <0x41600 0x80>;
466 msi-available-ranges = <0 0x100>;
476 interrupt-parent = <&mpic>;
482 reg = <0x30000 0x10000>;
484 interrupt-parent = <&mpic>;
485 fsl,num-channels = <4>;
486 fsl,channel-fifo-len = <24>;
487 fsl,exec-units-mask = <0x9fe>;
488 fsl,descriptor-types-mask = <0x3ab0ebf>;
492 interrupt-controller;
493 #address-cells = <0>;
494 #interrupt-cells = <2>;
495 reg = <0x40000 0x40000>;
496 compatible = "chrp,open-pic";
497 device_type = "open-pic";
501 compatible = "fsl,mpc8572-gpio";
502 reg = <0xf000 0x1000>;
504 interrupt-parent = <&mpic>;
505 #gpio-cells = <2>;
506 gpio-controller;
509 gpio-leds {
510 compatible = "gpio-leds";
515 linux,default-trigger = "heartbeat";
534 /* PME (pattern-matcher) */
536 compatible = "fsl,mpc8572-pme", "pme8572";
537 reg = <0x10000 0x5000>;
539 interrupt-parent = <&mpic>;
543 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
544 reg = <0x2f000 0x1000>;
546 interrupt-parent = <&mpic>;
550 compatible = "fsl,mpc8572-tlu", "fsl_tlu";
551 reg = <0x15000 0x1000>;
553 interrupt-parent = <&mpic>;
564 compatible = "fsl,mpc8548-pcie";
566 #interrupt-cells = <1>;
567 #size-cells = <2>;
568 #address-cells = <3>;
569 reg = <0 0xef009000 0 0x1000>;
570 bus-range = <0 255>;
573 clock-frequency = <33333333>;
574 interrupt-parent = <&mpic>;
576 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
577 interrupt-map = <
585 reg = <0x00000000 0x00000000 0x00000000 0x00000000 0x00000000>;
586 #size-cells = <2>;
587 #address-cells = <3>;
601 compatible = "fsl,mpc8548-pcie";
603 #interrupt-cells = <1>;
604 #size-cells = <2>;
605 #address-cells = <3>;
606 reg = <0 0xef00a000 0 0x1000>;
607 bus-range = <0 255>;
610 clock-frequency = <33333333>;
611 interrupt-parent = <&mpic>;
613 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
614 interrupt-map = <
622 reg = <0x0 0x0 0x0 0x0 0x0>;
623 #size-cells = <2>;
624 #address-cells = <3>;