Lines Matching +full:ucc +full:- +full:hdlc
36 reserved-memory {
37 #address-cells = <2>;
38 #size-cells = <2>;
41 bman_fbpr: bman-fbpr {
45 qman_fqd: qman-fqd {
49 qman_pfdr: qman-pfdr {
62 #address-cells = <1>;
63 #size-cells = <1>;
64 compatible = "cfi-flash";
66 bank-width = <2>;
67 device-width = <1>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 compatible = "fsl,ifc-nand";
78 compatible = "fsl,t1040d4rdb-cpld";
91 bportals: bman-portals@ff4000000 {
95 qportals: qman-portals@ff6000000 {
105 #address-cells = <1>;
106 #size-cells = <1>;
107 compatible = "micron,n25q512ax3", "jedec,spi-nor";
110 spi-max-frequency = <10000000>;
115 spi-max-frequency = <2000000>; /* input clock */
120 spi-max-frequency = <2000000>; /* input clock */
149 #address-cells = <1>;
150 #size-cells = <0>;
219 brg-frequency = <0>;
220 bus-frequency = <0>;
223 compatible = "fsl,t1040-qe-si";
228 compatible = "fsl,t1040-qe-siram";
232 ucc_hdlc: ucc@2000 {
233 compatible = "fsl,ucc-hdlc";
234 rx-clock-name = "clk8";
235 tx-clock-name = "clk9";
236 fsl,rx-sync-clock = "rsync_pin";
237 fsl,tx-sync-clock = "tsync_pin";
238 fsl,tx-timeslot-mask = <0xfffffffe>;
239 fsl,rx-timeslot-mask = <0xfffffffe>;
240 fsl,tdm-framer-type = "e1";
241 fsl,tdm-id = <0>;
242 fsl,siram-entry-id = <0>;
243 fsl,tdm-interface;
246 ucc_serial: ucc@2200 {
247 compatible = "fsl,t1040-ucc-uart";
248 port-number = <0>;
249 rx-clock-name = "brg2";
250 tx-clock-name = "brg2";