Lines Matching +full:p5020 +full:- +full:clockgen
2 * P5020/P5010 Silicon/SoC Device Tree Source (pre include)
4 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
35 /dts-v1/;
40 compatible = "fsl,P5020";
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
93 #address-cells = <1>;
94 #size-cells = <0>;
99 clocks = <&clockgen 1 0>;
100 next-level-cache = <&L2_0>;
101 fsl,portid-mapping = <0x80000000>;
102 L2_0: l2-cache {
103 next-level-cache = <&cpc>;
109 clocks = <&clockgen 1 1>;
110 next-level-cache = <&L2_1>;
111 fsl,portid-mapping = <0x40000000>;
112 L2_1: l2-cache {
113 next-level-cache = <&cpc>;