Lines Matching +full:0 +full:x0000000080000000
64 { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
68 { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
72 { 19, 1, 8 }, /* RDR 0 */
74 { 72, 2, 0 }, /* RDR 2 */
75 { 81, 2, 0 }, /* RDR 3 */
76 { 328, 6, 0 }, /* RDR 4 */
77 { 160, 3, 0 }, /* RDR 5 */
78 { 336, 6, 0 }, /* RDR 6 */
79 { 164, 3, 0 }, /* RDR 7 */
80 { 0, 0, 0 }, /* RDR 8 */
81 { 35, 1, 0 }, /* RDR 9 */
82 { 6, 1, 0 }, /* RDR 10 */
83 { 18, 1, 0 }, /* RDR 11 */
84 { 13, 1, 0 }, /* RDR 12 */
85 { 8, 1, 0 }, /* RDR 13 */
86 { 8, 1, 0 }, /* RDR 14 */
87 { 8, 1, 0 }, /* RDR 15 */
88 { 1530, 24, 0 }, /* RDR 16 */
89 { 16, 1, 0 }, /* RDR 17 */
90 { 4, 1, 0 }, /* RDR 18 */
91 { 0, 0, 0 }, /* RDR 19 */
96 { 71, 2, 0 }, /* RDR 24 */
97 { 71, 2, 0 }, /* RDR 25 */
98 { 11, 1, 0 }, /* RDR 26 */
99 { 18, 1, 0 }, /* RDR 27 */
100 { 128, 2, 0 }, /* RDR 28 */
101 { 0, 0, 0 }, /* RDR 29 */
102 { 16, 1, 0 }, /* RDR 30 */
103 { 16, 1, 0 }, /* RDR 31 */
108 { 19, 1, 8 }, /* RDR 0 */
110 { 20, 1, 0 }, /* RDR 2 */
111 { 0, 0, 0 }, /* RDR 3 */
112 { 344, 6, 0 }, /* RDR 4 */
113 { 176, 3, 0 }, /* RDR 5 */
114 { 336, 6, 0 }, /* RDR 6 */
115 { 0, 0, 0 }, /* RDR 7 */
116 { 0, 0, 0 }, /* RDR 8 */
117 { 0, 0, 0 }, /* RDR 9 */
118 { 28, 1, 0 }, /* RDR 10 */
119 { 33, 1, 0 }, /* RDR 11 */
120 { 0, 0, 0 }, /* RDR 12 */
121 { 230, 4, 0 }, /* RDR 13 */
122 { 32, 1, 0 }, /* RDR 14 */
123 { 128, 2, 0 }, /* RDR 15 */
124 { 1494, 24, 0 }, /* RDR 16 */
125 { 18, 1, 0 }, /* RDR 17 */
126 { 4, 1, 0 }, /* RDR 18 */
127 { 0, 0, 0 }, /* RDR 19 */
132 { 71, 2, 0 }, /* RDR 24 */
133 { 71, 2, 0 }, /* RDR 25 */
134 { 28, 1, 0 }, /* RDR 26 */
135 { 33, 1, 0 }, /* RDR 27 */
136 { 88, 2, 0 }, /* RDR 28 */
137 { 32, 1, 0 }, /* RDR 29 */
138 { 24, 1, 0 }, /* RDR 30 */
139 { 16, 1, 0 }, /* RDR 31 */
147 0x0000000000000000ul, /* first dbl word must be zero */
148 0xfdffe00000000000ul, /* RDR0 bitmask */
149 0x003f000000000000ul, /* RDR1 bitmask */
150 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (152 bits) */
151 0xfffffffffffffffful,
152 0xfffffffc00000000ul,
153 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (233 bits) */
154 0xfffffffffffffffful,
155 0xfffffffffffffffcul,
156 0xff00000000000000ul
164 0x0000000000000000ul, /* first dbl word must be zero */
165 0xfdffe00000000000ul, /* RDR0 bitmask */
166 0x003f000000000000ul, /* RDR1 bitmask */
167 0x00fffffffffffffful, /* RDR20-RDR21 bitmask (158 bits) */
168 0xfffffffffffffffful,
169 0xfffffffc00000000ul,
170 0xfffffffffffffffful, /* RDR22-RDR23 bitmask (210 bits) */
171 0xfffffffffffffffful,
172 0xfffffffffffffffful,
173 0xfffc000000000000ul
222 if (error != 0) { in perf_config()
230 if (error != 0) { in perf_config()
258 return 0; in perf_open()
267 perf_enabled = 0; in perf_release()
270 return 0; in perf_release()
278 return 0; in perf_read()
313 interface_type = (image_type >> 16) & 0xffff; in perf_write()
314 test = (image_type & 0xffff); in perf_write()
348 #if 0 /* FIXME!! */ in perf_patch_images()
358 * We can only use the lower 32-bits, the upper 32-bits should be 0 in perf_patch_images()
367 onyx_images[TLBMISS][15] &= 0xffffff00; in perf_patch_images()
369 onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); in perf_patch_images()
370 onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00; in perf_patch_images()
374 onyx_images[TLBHANDMISS][15] &= 0xffffff00; in perf_patch_images()
376 onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24)); in perf_patch_images()
377 onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00; in perf_patch_images()
381 onyx_images[BIG_CPI][15] &= 0xffffff00; in perf_patch_images()
383 onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24)); in perf_patch_images()
384 onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00; in perf_patch_images()
387 onyx_images[PANIC][15] &= 0xffffff00; /* clear last 2 bytes */ in perf_patch_images()
388 onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */ in perf_patch_images()
389 onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00; in perf_patch_images()
395 (cuda_images[TLBMISS][16]&0xffff0000) | in perf_patch_images()
396 ((dtlb_addr >> 8)&0x0000ffff); in perf_patch_images()
398 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); in perf_patch_images()
399 cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000; in perf_patch_images()
402 (cuda_images[TLBHANDMISS][16]&0xffff0000) | in perf_patch_images()
403 ((dtlb_addr >> 8)&0x0000ffff); in perf_patch_images()
405 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); in perf_patch_images()
406 cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000; in perf_patch_images()
409 (cuda_images[BIG_CPI][16]&0xffff0000) | in perf_patch_images()
410 ((dtlb_addr >> 8)&0x0000ffff); in perf_patch_images()
412 ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff); in perf_patch_images()
413 cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000; in perf_patch_images()
431 int error = 0; in perf_ioctl()
442 if (error_start != 0) { in perf_ioctl()
450 sizeof (raddr)) != 0) { in perf_ioctl()
523 cpu_device = per_cpu(cpu_data, 0).dev; in perf_init()
525 per_cpu(cpu_data, 0).dev->name); in perf_init()
527 return 0; in perf_init()
564 tmp64 = (userbuf[21] << 22) & 0x00000000ffc00000; in perf_stop_counters()
565 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff; in perf_stop_counters()
567 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000; in perf_stop_counters()
568 raddr[0] = (uint32_t)tmp64; in perf_stop_counters()
571 tmp64 = (userbuf[22] >> 9) & 0x00000000ffffffff; in perf_stop_counters()
573 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000; in perf_stop_counters()
577 tmp64 = (userbuf[22] << 24) & 0x00000000ff000000; in perf_stop_counters()
578 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff; in perf_stop_counters()
580 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000; in perf_stop_counters()
584 tmp64 = (userbuf[23] >> 7) & 0x00000000ffffffff; in perf_stop_counters()
586 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000; in perf_stop_counters()
600 userbuf[21] &= 0xfffffffffffffc00ul; /* 0 to last 10 bits */ in perf_stop_counters()
601 userbuf[22] = 0; in perf_stop_counters()
602 userbuf[23] = 0; in perf_stop_counters()
626 raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL); in perf_stop_counters()
627 raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL); in perf_stop_counters()
628 raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL); in perf_stop_counters()
629 raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL); in perf_stop_counters()
632 return 0; in perf_stop_counters()
657 uint64_t data, data_mask = 0; in perf_rdr_read_ubuf()
662 if ((width = tentry->width) == 0) in perf_rdr_read_ubuf()
663 return 0; in perf_rdr_read_ubuf()
668 buffer[i] = 0; in perf_rdr_read_ubuf()
672 if ((xbits = width & 0x03f) != 0) { in perf_rdr_read_ubuf()
712 if (tentry->width == 0) { in perf_rdr_clear()
719 perf_rdr_shift_out_U(rdr_num, 0UL); in perf_rdr_clear()
721 perf_rdr_shift_out_W(rdr_num, 0UL); in perf_rdr_clear()
725 return 0; in perf_rdr_clear()
765 bptr = &buffer[0]; in perf_write_image()
800 /* Merge intrigue bits into Runway STATUS 0 */ in perf_write_image()
801 tmp64 = __raw_readq(runway + RUNWAY_STATUS) & 0xffecfffffffffffful; in perf_write_image()
802 __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000ul), in perf_write_image()
806 for (i = 0; i < 8; i++) { in perf_write_image()
810 return 0; in perf_write_image()
826 if (tentry->width == 0) { return; } in perf_rdr_write()