Lines Matching full:l
30 l.movhi rd,hi(-KERNELBASE) ;\
31 l.add rd,rd,rs
34 l.movhi gpr,0x0
37 l.movhi gpr,hi(symbol) ;\
38 l.ori gpr,gpr,lo(symbol)
54 #define EMERGENCY_PRINT_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(14)
55 #define EMERGENCY_PRINT_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(14)
57 #define EMERGENCY_PRINT_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(15)
58 #define EMERGENCY_PRINT_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(15)
60 #define EMERGENCY_PRINT_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(16)
61 #define EMERGENCY_PRINT_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(16)
63 #define EMERGENCY_PRINT_STORE_GPR7 l.mtspr r0,r7,SPR_SHADOW_GPR(7)
64 #define EMERGENCY_PRINT_LOAD_GPR7 l.mfspr r7,r0,SPR_SHADOW_GPR(7)
66 #define EMERGENCY_PRINT_STORE_GPR8 l.mtspr r0,r8,SPR_SHADOW_GPR(8)
67 #define EMERGENCY_PRINT_LOAD_GPR8 l.mfspr r8,r0,SPR_SHADOW_GPR(8)
69 #define EMERGENCY_PRINT_STORE_GPR9 l.mtspr r0,r9,SPR_SHADOW_GPR(9)
70 #define EMERGENCY_PRINT_LOAD_GPR9 l.mfspr r9,r0,SPR_SHADOW_GPR(9)
73 #define EMERGENCY_PRINT_STORE_GPR4 l.sw 0x20(r0),r4
74 #define EMERGENCY_PRINT_LOAD_GPR4 l.lwz r4,0x20(r0)
76 #define EMERGENCY_PRINT_STORE_GPR5 l.sw 0x24(r0),r5
77 #define EMERGENCY_PRINT_LOAD_GPR5 l.lwz r5,0x24(r0)
79 #define EMERGENCY_PRINT_STORE_GPR6 l.sw 0x28(r0),r6
80 #define EMERGENCY_PRINT_LOAD_GPR6 l.lwz r6,0x28(r0)
82 #define EMERGENCY_PRINT_STORE_GPR7 l.sw 0x2c(r0),r7
83 #define EMERGENCY_PRINT_LOAD_GPR7 l.lwz r7,0x2c(r0)
85 #define EMERGENCY_PRINT_STORE_GPR8 l.sw 0x30(r0),r8
86 #define EMERGENCY_PRINT_LOAD_GPR8 l.lwz r8,0x30(r0)
88 #define EMERGENCY_PRINT_STORE_GPR9 l.sw 0x34(r0),r9
89 #define EMERGENCY_PRINT_LOAD_GPR9 l.lwz r9,0x34(r0)
97 #define EXCEPTION_STORE_GPR2 l.mtspr r0,r2,SPR_SHADOW_GPR(2)
98 #define EXCEPTION_LOAD_GPR2 l.mfspr r2,r0,SPR_SHADOW_GPR(2)
100 #define EXCEPTION_STORE_GPR3 l.mtspr r0,r3,SPR_SHADOW_GPR(3)
101 #define EXCEPTION_LOAD_GPR3 l.mfspr r3,r0,SPR_SHADOW_GPR(3)
103 #define EXCEPTION_STORE_GPR4 l.mtspr r0,r4,SPR_SHADOW_GPR(4)
104 #define EXCEPTION_LOAD_GPR4 l.mfspr r4,r0,SPR_SHADOW_GPR(4)
106 #define EXCEPTION_STORE_GPR5 l.mtspr r0,r5,SPR_SHADOW_GPR(5)
107 #define EXCEPTION_LOAD_GPR5 l.mfspr r5,r0,SPR_SHADOW_GPR(5)
109 #define EXCEPTION_STORE_GPR6 l.mtspr r0,r6,SPR_SHADOW_GPR(6)
110 #define EXCEPTION_LOAD_GPR6 l.mfspr r6,r0,SPR_SHADOW_GPR(6)
113 #define EXCEPTION_STORE_GPR2 l.sw 0x64(r0),r2
114 #define EXCEPTION_LOAD_GPR2 l.lwz r2,0x64(r0)
116 #define EXCEPTION_STORE_GPR3 l.sw 0x68(r0),r3
117 #define EXCEPTION_LOAD_GPR3 l.lwz r3,0x68(r0)
119 #define EXCEPTION_STORE_GPR4 l.sw 0x6c(r0),r4
120 #define EXCEPTION_LOAD_GPR4 l.lwz r4,0x6c(r0)
122 #define EXCEPTION_STORE_GPR5 l.sw 0x70(r0),r5
123 #define EXCEPTION_LOAD_GPR5 l.lwz r5,0x70(r0)
125 #define EXCEPTION_STORE_GPR6 l.sw 0x74(r0),r6
126 #define EXCEPTION_LOAD_GPR6 l.lwz r6,0x74(r0)
135 #define EXCEPTION_T_STORE_GPR30 l.mtspr r0,r30,SPR_SHADOW_GPR(30)
136 #define EXCEPTION_T_LOAD_GPR30(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(30)
138 #define EXCEPTION_T_STORE_GPR10 l.mtspr r0,r10,SPR_SHADOW_GPR(10)
139 #define EXCEPTION_T_LOAD_GPR10(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(10)
141 #define EXCEPTION_T_STORE_SP l.mtspr r0,r1,SPR_SHADOW_GPR(1)
142 #define EXCEPTION_T_LOAD_SP(reg) l.mfspr reg,r0,SPR_SHADOW_GPR(1)
145 #define EXCEPTION_T_STORE_GPR30 l.sw 0x78(r0),r30
146 #define EXCEPTION_T_LOAD_GPR30(reg) l.lwz reg,0x78(r0)
148 #define EXCEPTION_T_STORE_GPR10 l.sw 0x7c(r0),r10
149 #define EXCEPTION_T_LOAD_GPR10(reg) l.lwz reg,0x7c(r0)
151 #define EXCEPTION_T_STORE_SP l.sw 0x80(r0),r1
152 #define EXCEPTION_T_LOAD_SP(reg) l.lwz reg,0x80(r0)
160 l.mfspr t1,r0,SPR_COREID ;\
161 l.slli t1,t1,2 ;\
162 l.add reg,reg,t1 ;\
164 l.lwz reg,0(t1)
169 l.lwz reg,0(t1)
177 l.mfspr r10,r0,SPR_COREID ;\
178 l.slli r10,r10,2 ;\
179 l.add r30,r30,r10 ;\
181 l.lwz r10,0(r30)
187 l.lwz r10,0(r30)
223 l.mfspr r30,r0,SPR_ESR_BASE ;\
224 l.andi r30,r30,SPR_SR_SM ;\
225 l.sfeqi r30,0 ;\
227 l.bnf 2f /* kernel_mode */ ;\
232 l.lwz r1,(TI_KSP)(r30) ;\
238 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
241 l.sw PT_GPR12(r30),r12 ;\
243 l.mfspr r12,r0,SPR_EPCR_BASE ;\
244 l.sw PT_PC(r30),r12 ;\
245 l.mfspr r12,r0,SPR_ESR_BASE ;\
246 l.sw PT_SR(r30),r12 ;\
249 l.sw PT_GPR30(r30),r12 ;\
252 l.sw PT_GPR10(r30),r12 ;\
255 l.sw PT_SP(r30),r12 ;\
257 l.sw PT_GPR4(r30),r4 ;\
258 l.mfspr r4,r0,SPR_EEAR_BASE ;\
263 l.mfspr r30,r0,SPR_SR ;\
264 l.andi r30,r30,SPR_SR_DSX ;\
265 l.ori r30,r30,(EXCEPTION_SR) ;\
266 l.mtspr r0,r30,SPR_ESR_BASE ;\
269 l.mtspr r0,r30,SPR_EPCR_BASE ;\
270 l.rfe
278 * l.ori r3,r0,0x1 ;\
279 * l.mtspr r0,r3,SPR_SR ;\
280 * l.movhi r3,hi(0xf0000100) ;\
281 * l.ori r3,r3,lo(0xf0000100) ;\
282 * l.jr r3 ;\
283 * l.nop 1
298 l.addi r1,r3,0x0 ;\
299 l.addi r10,r9,0x0 ;\
302 l.jal _emergency_print ;\
303 l.nop ;\
304 l.mfspr r3,r0,SPR_NPC ;\
305 l.jal _emergency_print_nr ;\
306 l.andi r3,r3,0x1f00 ;\
309 l.jal _emergency_print ;\
310 l.nop ;\
311 l.jal _emergency_print_nr ;\
312 l.mfspr r3,r0,SPR_EPCR_BASE ;\
315 l.jal _emergency_print ;\
316 l.nop ;\
318 l.addi r3,r1,0x0 ;\
319 l.addi r9,r10,0x0 ;\
326 l.addi r1,r1,-(INT_FRAME_SIZE) ;\
329 l.sw PT_GPR12(r30),r12 ;\
330 l.mfspr r12,r0,SPR_EPCR_BASE ;\
331 l.sw PT_PC(r30),r12 ;\
332 l.mfspr r12,r0,SPR_ESR_BASE ;\
333 l.sw PT_SR(r30),r12 ;\
336 l.sw PT_GPR30(r30),r12 ;\
339 l.sw PT_GPR10(r30),r12 ;\
342 l.sw PT_SP(r30),r12 ;\
343 l.sw PT_GPR13(r30),r13 ;\
346 l.sw PT_GPR4(r30),r4 ;\
347 l.mfspr r4,r0,SPR_EEAR_BASE ;\
351 l.ori r30,r0,(EXCEPTION_SR) ;\
352 l.mtspr r0,r30,SPR_ESR_BASE ;\
355 l.mtspr r0,r30,SPR_EPCR_BASE ;\
356 l.rfe
369 l.jr r13
370 l.nop
381 // l.mtspr r0,r0,SPR_TTMR
390 // l.mtspr r0,r0,SPR_TTMR
413 l.j boot_dtlb_miss_handler
414 l.nop
418 l.j boot_itlb_miss_handler
419 l.nop
521 l.or r25,r0,r3 /* pointer to fdt */
527 l.ori r3,r0,0x1
528 l.mtspr r0,r3,SPR_SR
536 l.movhi r3,hi(SPR_TTMR_CR)
537 l.mtspr r0,r3,SPR_TTMR
571 l.mfspr r26,r0,SPR_COREID
572 l.sfeq r26,r0
573 l.bnf secondary_wait
574 l.nop
583 l.sw TI_KSP(r31), r1
585 l.ori r4,r0,0x0
600 l.sw (0)(r28),r0
601 l.sfltu r28,r30
602 l.bf 1b
603 l.addi r28,r28,4
606 l.jal _ic_enable
607 l.nop
610 l.jal _dc_enable
611 l.nop
614 l.jal _flush_tlb
615 l.nop
624 l.mfspr r30,r0,SPR_SR
625 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
626 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
627 l.or r30,r30,r28
628 l.mtspr r0,r30,SPR_SR
629 l.nop
630 l.nop
631 l.nop
632 l.nop
633 l.nop
634 l.nop
635 l.nop
636 l.nop
637 l.nop
638 l.nop
639 l.nop
640 l.nop
641 l.nop
642 l.nop
643 l.nop
644 l.nop
647 l.nop 5
650 l.lwz r3,0(r25) /* load magic from fdt into r3 */
651 l.movhi r4,hi(OF_DT_HEADER)
652 l.ori r4,r4,lo(OF_DT_HEADER)
653 l.sfeq r3,r4
654 l.bf _fdt_found
655 l.nop
657 l.or r25,r0,r0
660 l.or r3,r0,r25
662 l.jalr r24
663 l.nop
704 l.jr r30
705 l.nop
709 * I N V A L I D A T E T L B e n t r i e s
713 l.addi r7,r0,128 /* Maximum number of sets */
715 l.mtspr r5,r0,0x0
716 l.mtspr r6,r0,0x0
718 l.addi r5,r5,1
719 l.addi r6,r6,1
720 l.sfeq r7,r0
721 l.bnf 1b
722 l.addi r7,r7,-1
724 l.jr r9
725 l.nop
731 l.mfspr r25,r0,SPR_UPR
732 l.andi r25,r25,SPR_UPR_PMP
733 l.sfeq r25,r0
734 l.bf secondary_check_release
735 l.nop
740 l.mtspr r0,r25,SPR_EVBAR
743 l.mfspr r25,r0,SPR_SR
744 l.ori r25,r25,SPR_SR_IEE
745 l.mtspr r0,r25,SPR_SR
748 l.mfspr r25,r0,SPR_PICMR
749 l.ori r25,r25,0xffff
750 l.mtspr r0,r25,SPR_PICMR
753 l.mfspr r25,r0,SPR_PMR
755 l.or r25,r25,r3
756 l.mtspr r0,r25,SPR_PMR
759 l.mtspr r0,r0,SPR_EVBAR
766 l.mfspr r25,r0,SPR_COREID
769 l.lwz r3,0(r4)
770 l.sfeq r25,r3
771 l.bnf secondary_wait
772 l.nop
781 l.lwz r10,0(r30)
782 l.addi r1,r10,THREAD_SIZE
784 l.sw TI_KSP(r30),r1
786 l.jal _ic_enable
787 l.nop
789 l.jal _dc_enable
790 l.nop
792 l.jal _flush_tlb
793 l.nop
798 l.mfspr r30,r0,SPR_SR
799 l.movhi r28,hi(SPR_SR_DME | SPR_SR_IME)
800 l.ori r28,r28,lo(SPR_SR_DME | SPR_SR_IME)
801 l.or r30,r30,r28
806 * Then EPCR is set to secondary_start and then a l.rfe is issued to
809 l.mtspr r0,r30,SPR_ESR_BASE
811 l.mtspr r0,r30,SPR_EPCR_BASE
812 l.rfe
816 l.jr r30
817 l.nop
830 l.mfspr r24,r0,SPR_UPR
831 l.andi r26,r24,SPR_UPR_ICP
832 l.sfeq r26,r0
833 l.bf 9f
834 l.nop
837 l.mfspr r6,r0,SPR_SR
838 l.addi r5,r0,-1
839 l.xori r5,r5,SPR_SR_ICE
840 l.and r5,r6,r5
841 l.mtspr r0,r5,SPR_SR
848 l.mfspr r24,r0,SPR_ICCFGR
849 l.andi r26,r24,SPR_ICCFGR_CBS
850 l.srli r28,r26,7
851 l.ori r30,r0,16
852 l.sll r14,r30,r28
858 l.andi r26,r24,SPR_ICCFGR_NCS
859 l.srli r28,r26,3
860 l.ori r30,r0,1
861 l.sll r16,r30,r28
864 l.addi r6,r0,0
865 l.sll r5,r14,r28
866 // l.mul r5,r14,r16
867 // l.trap 1
868 // l.addi r5,r0,IC_SIZE
870 l.mtspr r0,r6,SPR_ICBIR
871 l.sfne r6,r5
872 l.bf 1b
873 l.add r6,r6,r14
874 // l.addi r6,r6,IC_LINE
877 l.mfspr r6,r0,SPR_SR
878 l.ori r6,r6,SPR_SR_ICE
879 l.mtspr r0,r6,SPR_SR
880 l.nop
881 l.nop
882 l.nop
883 l.nop
884 l.nop
885 l.nop
886 l.nop
887 l.nop
888 l.nop
889 l.nop
891 l.jr r9
892 l.nop
896 l.mfspr r24,r0,SPR_UPR
897 l.andi r26,r24,SPR_UPR_DCP
898 l.sfeq r26,r0
899 l.bf 9f
900 l.nop
903 l.mfspr r6,r0,SPR_SR
904 l.addi r5,r0,-1
905 l.xori r5,r5,SPR_SR_DCE
906 l.and r5,r6,r5
907 l.mtspr r0,r5,SPR_SR
914 l.mfspr r24,r0,SPR_DCCFGR
915 l.andi r26,r24,SPR_DCCFGR_CBS
916 l.srli r28,r26,7
917 l.ori r30,r0,16
918 l.sll r14,r30,r28
924 l.andi r26,r24,SPR_DCCFGR_NCS
925 l.srli r28,r26,3
926 l.ori r30,r0,1
927 l.sll r16,r30,r28
930 l.addi r6,r0,0
931 l.sll r5,r14,r28
933 l.mtspr r0,r6,SPR_DCBIR
934 l.sfne r6,r5
935 l.bf 1b
936 l.add r6,r6,r14
939 l.mfspr r6,r0,SPR_SR
940 l.ori r6,r6,SPR_SR_DCE
941 l.mtspr r0,r6,SPR_SR
943 l.jr r9
944 l.nop
985 l.mfspr r6,r0,SPR_ESR_BASE //
986 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
987 l.sfeqi r6,0 // r6 == 0x1 --> SM
988 l.bf exit_with_no_dtranslation //
989 l.nop
1002 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1007 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VPN…
1009 l.mfspr r6, r0, SPR_DMMUCFGR
1010 l.andi r6, r6, SPR_DMMUCFGR_NTS
1011 l.srli r6, r6, SPR_DMMUCFGR_NTS_OFF
1012 l.ori r5, r0, 0x1
1013 l.sll r5, r5, r6 // r5 = number DMMU sets
1014 l.addi r6, r5, -1 // r6 = nsets mask
1015 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1017 l.or r6,r6,r4 // r6 <- r4
1018 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1019 l.movhi r5,hi(DTLB_MR_MASK) // r5 <- ffff:0000.x000
1020 l.ori r5,r5,lo(DTLB_MR_MASK) // r5 <- ffff:1111.x001 - apply DTLB_MR_MASK
1021 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have DTLBMR entry
1022 l.mtspr r2,r5,SPR_DTLBMR_BASE(0) // set DTLBMR
1026 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xbfffffff >= EA)
1027 l.bf 1f // goto out
1028 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1032 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1033 l.movhi r5,hi(DTLB_TR_MASK) // r5 <- ffff:0000.x000
1034 l.ori r5,r5,lo(DTLB_TR_MASK) // r5 <- ffff:1111.x330 - apply DTLB_MR_MASK
1035 l.and r5,r5,r3 // r5 <- PPN :PPN .x330 - we have DTLBTR entry
1036 l.mtspr r2,r5,SPR_DTLBTR_BASE(0) // set DTLBTR
1044 l.rfe // SR <- ESR, PC <- EPC
1050 l.j _dispatch_bus_fault
1081 l.mfspr r6,r0,SPR_ESR_BASE //
1082 l.andi r6,r6,SPR_SR_SM // are we in kernel mode ?
1083 l.sfeqi r6,0 // r6 == 0x1 --> SM
1084 l.bf exit_with_no_itranslation
1085 l.nop
1089 l.mfspr r4,r0,SPR_EEAR_BASE // get the offending EA
1094 …l.srli r3,r4,0xd // r3 <- r4 / 8192 (sets are relative to page size (8Kb) NOT VP…
1096 l.mfspr r6, r0, SPR_IMMUCFGR
1097 l.andi r6, r6, SPR_IMMUCFGR_NTS
1098 l.srli r6, r6, SPR_IMMUCFGR_NTS_OFF
1099 l.ori r5, r0, 0x1
1100 l.sll r5, r5, r6 // r5 = number IMMU sets from IMMUCFGR
1101 l.addi r6, r5, -1 // r6 = nsets mask
1102 l.and r2, r3, r6 // r2 <- r3 % NSETS_MASK
1104 l.or r6,r6,r4 // r6 <- r4
1105 l.ori r6,r6,~(VPN_MASK) // r6 <- VPN :VPN .xfff - clear up lo(r6) to 0x**** *fff
1106 l.movhi r5,hi(ITLB_MR_MASK) // r5 <- ffff:0000.x000
1107 l.ori r5,r5,lo(ITLB_MR_MASK) // r5 <- ffff:1111.x001 - apply ITLB_MR_MASK
1108 l.and r5,r5,r6 // r5 <- VPN :VPN .x001 - we have ITLBMR entry
1109 l.mtspr r2,r5,SPR_ITLBMR_BASE(0) // set ITLBMR
1119 l.sfgeu r6,r4 // flag if r6 >= r4 (if 0xb0ffffff >= EA)
1120 l.bf 1f // goto out
1121 l.and r3,r4,r4 // delay slot :: 24 <- r4 (if flag==1)
1125 l.ori r3,r3,~(PPN_MASK) // r3 <- PPN :PPN .xfff - clear up lo(r6) to 0x**** *fff
1126 l.movhi r5,hi(ITLB_TR_MASK) // r5 <- ffff:0000.x000
1127 l.ori r5,r5,lo(ITLB_TR_MASK) // r5 <- ffff:1111.x050 - apply ITLB_MR_MASK
1128 l.and r5,r5,r3 // r5 <- PPN :PPN .x050 - we have ITLBTR entry
1129 l.mtspr r2,r5,SPR_ITLBTR_BASE(0) // set ITLBTR
1137 l.rfe // SR <- ESR, PC <- EPC
1142 l.j _dispatch_bus_fault
1143 l.nop
1168 l.mfspr r2,r0,SPR_EEAR_BASE
1173 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1174 l.slli r4,r4,0x2 // to get address << 2
1175 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1181 l.lwz r3,0x0(r4) // get *pmd value
1182 l.sfne r3,r0
1183 l.bnf d_pmd_none
1184 l.addi r3,r0,0xffffe000 // PAGE_MASK
1190 l.lwz r4,0x0(r4) // get **pmd value
1191 l.and r4,r4,r3 // & PAGE_MASK
1192 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1193 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1194 l.slli r3,r3,0x2 // to get address << 2
1195 l.add r3,r3,r4
1196 l.lwz r3,0x0(r3) // this is pte at last
1200 l.andi r4,r3,0x1
1201 l.sfne r4,r0 // is pte present
1202 l.bnf d_pte_not_present
1203 l.addi r4,r0,0xffffe3fa // PAGE_MASK | DTLB_UP_CONVERT_MASK
1207 l.and r4,r3,r4 // apply the mask
1209 l.mfspr r2, r0, SPR_DMMUCFGR
1210 l.andi r2, r2, SPR_DMMUCFGR_NTS
1211 l.srli r2, r2, SPR_DMMUCFGR_NTS_OFF
1212 l.ori r3, r0, 0x1
1213 l.sll r3, r3, r2 // r3 = number DMMU sets DMMUCFGR
1214 l.addi r2, r3, -1 // r2 = nsets mask
1215 l.mfspr r3, r0, SPR_EEAR_BASE
1216 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1217 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1219 l.mtspr r2,r4,SPR_DTLBTR_BASE(0)
1223 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1224 l.ori r4,r3,0x1 // set hardware valid bit: DTBL_MR entry
1225 l.mtspr r2,r4,SPR_DTLBMR_BASE(0)
1230 l.rfe
1246 l.mfspr r2,r0,SPR_EEAR_BASE
1253 l.srli r4,r2,0x18 // >> PAGE_SHIFT + (PAGE_SHIFT - 2)
1254 l.slli r4,r4,0x2 // to get address << 2
1255 l.add r3,r4,r3 // r4 is pgd_index(daddr)
1261 l.lwz r3,0x0(r4) // get *pmd value
1262 l.sfne r3,r0
1263 l.bnf i_pmd_none
1264 l.addi r3,r0,0xffffe000 // PAGE_MASK
1271 l.lwz r4,0x0(r4) // get **pmd value
1272 l.and r4,r4,r3 // & PAGE_MASK
1273 l.srli r2,r2,0xd // >> PAGE_SHIFT, r2 == EEAR
1274 l.andi r3,r2,0x7ff // (1UL << PAGE_SHIFT - 2) - 1
1275 l.slli r3,r3,0x2 // to get address << 2
1276 l.add r3,r3,r4
1277 l.lwz r3,0x0(r3) // this is pte at last
1282 l.andi r4,r3,0x1
1283 l.sfne r4,r0 // is pte present
1284 l.bnf i_pte_not_present
1285 l.addi r4,r0,0xffffe03a // PAGE_MASK | ITLB_UP_CONVERT_MASK
1289 l.and r4,r3,r4 // apply the mask
1290 l.andi r3,r3,0x7c0 // _PAGE_EXEC | _PAGE_SRE | _PAGE_SWE | _PAGE_URE | _PAGE_UWE
1291 l.sfeq r3,r0
1292 l.bf itlb_tr_fill //_workaround
1294 l.mfspr r2, r0, SPR_IMMUCFGR
1295 l.andi r2, r2, SPR_IMMUCFGR_NTS
1296 l.srli r2, r2, SPR_IMMUCFGR_NTS_OFF
1297 l.ori r3, r0, 0x1
1298 l.sll r3, r3, r2 // r3 = number IMMU sets IMMUCFGR
1299 l.addi r2, r3, -1 // r2 = nsets mask
1300 l.mfspr r3, r0, SPR_EEAR_BASE
1301 l.srli r3, r3, 0xd // >> PAGE_SHIFT
1302 l.and r2, r3, r2 // calc offset: & (NUM_TLB_ENTRIES-1)
1312 l.ori r4,r4,0xc0 // | (SPR_ITLBTR_UXE | ITLBTR_SXE)
1314 l.mtspr r2,r4,SPR_ITLBTR_BASE(0)
1318 l.slli r3, r3, 0xd /* << PAGE_SHIFT => EA & PAGE_MASK */
1319 l.ori r4,r3,0x1 // set hardware valid bit: ITBL_MR entry
1320 l.mtspr r2,r4,SPR_ITLBMR_BASE(0)
1325 l.rfe
1357 l.movhi r4,hi(UART_BASE_ADD)
1358 l.ori r4,r4,lo(UART_BASE_ADD)
1362 1: l.lwz r5,4(r4)
1363 l.andi r5,r5,0xff
1364 l.sfnei r5,0
1365 l.bf 1b
1366 l.nop
1369 l.andi r7,r7,0xff
1370 l.sw 0(r4),r7
1373 l.addi r6,r0,0x20
1374 1: l.lbz r5,5(r4)
1375 l.andi r5,r5,0x20
1376 l.sfeq r5,r6
1377 l.bnf 1b
1378 l.nop
1381 l.sb 0(r4),r7
1384 l.addi r6,r0,0x60
1385 1: l.lbz r5,5(r4)
1386 l.andi r5,r5,0x60
1387 l.sfeq r5,r6
1388 l.bnf 1b
1389 l.nop
1394 l.jr r9
1395 l.nop
1412 2: l.lbz r7,0(r3)
1413 l.sfeqi r7,0x0
1414 l.bf 9f
1415 l.nop
1417 l.jal _emergency_putc
1418 l.nop
1421 l.j 2b
1422 l.addi r3,r3,0x1
1427 l.jr r9
1428 l.nop
1444 l.addi r8,r0,32 // shift register
1447 l.addi r8,r8,-0x4
1448 l.srl r7,r3,r8
1449 l.andi r7,r7,0xf
1452 l.sfeqi r8,0x4
1453 l.bf 2f
1454 l.nop
1456 l.sfeq r7,r0
1457 l.bf 1b
1458 l.nop
1461 l.srl r7,r3,r8
1463 l.andi r7,r7,0xf
1464 l.sflts r8,r0
1465 l.bf 9f
1468 l.sfgtui r7,0x9
1469 l.bnf 8f
1470 l.nop
1471 l.addi r7,r7,0x27
1474 8: l.jal _emergency_putc
1475 l.addi r7,r7,0x30
1478 l.j 2b
1479 l.addi r8,r8,-0x4
1485 l.jr r9
1486 l.nop
1510 l.movhi r3,hi(UART_BASE_ADD)
1511 l.ori r3,r3,lo(UART_BASE_ADD)
1514 l.addi r4,r0,0x7
1515 l.sb 0x2(r3),r4
1517 l.addi r4,r0,0x0
1518 l.sb 0x1(r3),r4
1520 l.addi r4,r0,0x3
1521 l.sb 0x3(r3),r4
1523 l.lbz r5,3(r3)
1524 l.ori r4,r5,0x80
1525 l.sb 0x3(r3),r4
1526 l.addi r4,r0,((UART_DIVISOR>>8) & 0x000000ff)
1527 l.sb UART_DLM(r3),r4
1528 l.addi r4,r0,((UART_DIVISOR) & 0x000000ff)
1529 l.sb UART_DLL(r3),r4
1530 l.sb 0x3(r3),r5
1533 l.jr r9
1534 l.nop
1542 l.ori r3,r0,SPR_SR_SM
1543 l.mtspr r0,r3,SPR_ESR_BASE
1544 l.rfe