Lines Matching full:l
28 l.mfspr t2,r0,SPR_SR ;\
29 l.movhi t1,hi(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
30 l.ori t1,t1,lo(~(SPR_SR_IEE|SPR_SR_TEE)) ;\
31 l.and t2,t2,t1 ;\
32 l.mtspr r0,t2,SPR_SR
35 l.mfspr t1,r0,SPR_SR ;\
36 l.ori t1,t1,lo(SPR_SR_IEE|SPR_SR_TEE) ;\
37 l.mtspr r0,t1,SPR_SR
46 l.sw -8(r1),r2 /* store frame pointer */ ;\
47 l.sw -4(r1),r9 /* store return address */ ;\
48 l.addi r2,r1,0 /* move sp to fp */ ;\
49 l.jal trace_op ;\
50 l.addi r1,r1,-8 ;\
51 l.ori r1,r2,0 /* restore sp */ ;\
52 l.lwz r9,-4(r1) /* restore return address */ ;\
53 l.lwz r2,-8(r1) /* restore fp */ ;\
59 l.sw -12(r1),t1 /* save extra reg */ ;\
60 l.sw -8(r1),r2 /* store frame pointer */ ;\
61 l.sw -4(r1),r9 /* store return address */ ;\
62 l.addi r2,r1,0 /* move sp to fp */ ;\
63 l.jal trace_op ;\
64 l.addi r1,r1,-12 ;\
65 l.ori r1,r2,0 /* restore sp */ ;\
66 l.lwz r9,-4(r1) /* restore return address */ ;\
67 l.lwz r2,-8(r1) /* restore fp */ ;\
68 l.lwz t1,-12(r1) /* restore extra reg */
74 l.lwz r3,PT_GPR3(r1) ;\
75 l.lwz r4,PT_GPR4(r1) ;\
76 l.lwz r5,PT_GPR5(r1) ;\
77 l.lwz r6,PT_GPR6(r1) ;\
78 l.lwz r7,PT_GPR7(r1) ;\
79 l.lwz r8,PT_GPR8(r1) ;\
80 l.lwz r11,PT_GPR11(r1)
82 l.lwz r5,PT_SR(r1) ;\
83 l.andi r3,r5,(SPR_SR_IEE|SPR_SR_TEE) ;\
84 l.sfeq r5,r0 /* skip trace if irqs were already off */;\
85 l.bf 1f ;\
86 l.nop ;\
105 l.lwz r3,PT_PC(r1) ;\
106 l.mtspr r0,r3,SPR_EPCR_BASE ;\
107 l.lwz r3,PT_SR(r1) ;\
108 l.mtspr r0,r3,SPR_ESR_BASE ;\
109 l.lwz r2,PT_GPR2(r1) ;\
110 l.lwz r3,PT_GPR3(r1) ;\
111 l.lwz r4,PT_GPR4(r1) ;\
112 l.lwz r5,PT_GPR5(r1) ;\
113 l.lwz r6,PT_GPR6(r1) ;\
114 l.lwz r7,PT_GPR7(r1) ;\
115 l.lwz r8,PT_GPR8(r1) ;\
116 l.lwz r9,PT_GPR9(r1) ;\
117 l.lwz r10,PT_GPR10(r1) ;\
118 l.lwz r11,PT_GPR11(r1) ;\
119 l.lwz r12,PT_GPR12(r1) ;\
120 l.lwz r13,PT_GPR13(r1) ;\
121 l.lwz r14,PT_GPR14(r1) ;\
122 l.lwz r15,PT_GPR15(r1) ;\
123 l.lwz r16,PT_GPR16(r1) ;\
124 l.lwz r17,PT_GPR17(r1) ;\
125 l.lwz r18,PT_GPR18(r1) ;\
126 l.lwz r19,PT_GPR19(r1) ;\
127 l.lwz r20,PT_GPR20(r1) ;\
128 l.lwz r21,PT_GPR21(r1) ;\
129 l.lwz r22,PT_GPR22(r1) ;\
130 l.lwz r23,PT_GPR23(r1) ;\
131 l.lwz r24,PT_GPR24(r1) ;\
132 l.lwz r25,PT_GPR25(r1) ;\
133 l.lwz r26,PT_GPR26(r1) ;\
134 l.lwz r27,PT_GPR27(r1) ;\
135 l.lwz r28,PT_GPR28(r1) ;\
136 l.lwz r29,PT_GPR29(r1) ;\
137 l.lwz r30,PT_GPR30(r1) ;\
138 l.lwz r31,PT_GPR31(r1) ;\
139 l.lwz r1,PT_SP(r1) ;\
140 l.rfe
147 l.sw PT_GPR2(r1),r2 ;\
148 l.sw PT_GPR3(r1),r3 ;\
150 l.sw PT_GPR5(r1),r5 ;\
151 l.sw PT_GPR6(r1),r6 ;\
152 l.sw PT_GPR7(r1),r7 ;\
153 l.sw PT_GPR8(r1),r8 ;\
154 l.sw PT_GPR9(r1),r9 ;\
156 l.sw PT_GPR11(r1),r11 ;\
158 l.sw PT_GPR13(r1),r13 ;\
159 l.sw PT_GPR14(r1),r14 ;\
160 l.sw PT_GPR15(r1),r15 ;\
161 l.sw PT_GPR16(r1),r16 ;\
162 l.sw PT_GPR17(r1),r17 ;\
163 l.sw PT_GPR18(r1),r18 ;\
164 l.sw PT_GPR19(r1),r19 ;\
165 l.sw PT_GPR20(r1),r20 ;\
166 l.sw PT_GPR21(r1),r21 ;\
167 l.sw PT_GPR22(r1),r22 ;\
168 l.sw PT_GPR23(r1),r23 ;\
169 l.sw PT_GPR24(r1),r24 ;\
170 l.sw PT_GPR25(r1),r25 ;\
171 l.sw PT_GPR26(r1),r26 ;\
172 l.sw PT_GPR27(r1),r27 ;\
173 l.sw PT_GPR28(r1),r28 ;\
174 l.sw PT_GPR29(r1),r29 ;\
176 l.sw PT_GPR31(r1),r31 ;\
179 l.addi r30,r0,-1 ;\
180 l.sw PT_ORIG_GPR11(r1),r30
186 l.sw PT_GPR2(r1),r2 ;\
187 l.sw PT_GPR3(r1),r3 ;\
188 l.sw PT_GPR5(r1),r5 ;\
189 l.sw PT_GPR6(r1),r6 ;\
190 l.sw PT_GPR7(r1),r7 ;\
191 l.sw PT_GPR8(r1),r8 ;\
192 l.sw PT_GPR9(r1),r9 ;\
194 l.sw PT_GPR11(r1),r11 ;\
196 l.sw PT_GPR13(r1),r13 ;\
197 l.sw PT_GPR14(r1),r14 ;\
198 l.sw PT_GPR15(r1),r15 ;\
199 l.sw PT_GPR16(r1),r16 ;\
200 l.sw PT_GPR17(r1),r17 ;\
201 l.sw PT_GPR18(r1),r18 ;\
202 l.sw PT_GPR19(r1),r19 ;\
203 l.sw PT_GPR20(r1),r20 ;\
204 l.sw PT_GPR21(r1),r21 ;\
205 l.sw PT_GPR22(r1),r22 ;\
206 l.sw PT_GPR23(r1),r23 ;\
207 l.sw PT_GPR24(r1),r24 ;\
208 l.sw PT_GPR25(r1),r25 ;\
209 l.sw PT_GPR26(r1),r26 ;\
210 l.sw PT_GPR27(r1),r27 ;\
211 l.sw PT_GPR28(r1),r28 ;\
212 l.sw PT_GPR29(r1),r29 ;\
214 l.sw PT_GPR31(r1),r31 ;\
216 l.addi r30,r0,-1 ;\
217 l.sw PT_ORIG_GPR11(r1),r30 ;\
218 l.addi r3,r1,0 ;\
220 l.addi r5,r0,vector ;\
221 l.jal unhandled_exception ;\
222 l.nop ;\
223 l.j _ret_from_exception ;\
224 l.nop
228 l.movhi reg,hi(lwa_flag) ;\
229 l.ori reg,reg,lo(lwa_flag) ;\
230 l.sw 0(reg),r0
247 l.jal _start
248 l.andi r0,r0,0
255 l.jal do_bus_fault
256 l.addi r3,r1,0 /* pt_regs */
258 l.j _ret_from_exception
259 l.nop
264 l.and r5,r5,r0
265 l.j 1f
266 l.nop
271 l.ori r5,r0,0x300 // exception vector
273 l.addi r3,r1,0 // pt_regs
277 l.lwz r6,PT_PC(r3) // address of an offending insn
278 l.lwz r6,0(r6) // instruction that caused pf
280 l.srli r6,r6,26 // check opcode for jump insn
281 l.sfeqi r6,0 // l.j
282 l.bf 8f
283 l.sfeqi r6,1 // l.jal
284 l.bf 8f
285 l.sfeqi r6,3 // l.bnf
286 l.bf 8f
287 l.sfeqi r6,4 // l.bf
288 l.bf 8f
289 l.sfeqi r6,0x11 // l.jr
290 l.bf 8f
291 l.sfeqi r6,0x12 // l.jalr
292 l.bf 8f
293 l.nop
295 l.j 9f
296 l.nop
299 l.lwz r6,PT_PC(r3) // address of an offending insn
300 l.addi r6,r6,4
301 l.lwz r6,0(r6) // instruction that caused pf
302 l.srli r6,r6,26 // get opcode
307 l.mfspr r6,r0,SPR_SR // SR
308 l.andi r6,r6,SPR_SR_DSX // check for delay slot exception
309 l.sfne r6,r0 // exception happened in delay slot
310 l.bnf 7f
311 l.lwz r6,PT_PC(r3) // address of an offending insn
313 l.addi r6,r6,4 // offending insn is in delay slot
315 l.lwz r6,0(r6) // instruction that caused pf
316 l.srli r6,r6,26 // check opcode for write access
319 l.sfgeui r6,0x33 // check opcode for write access
320 l.bnf 1f
321 l.sfleui r6,0x37
322 l.bnf 1f
323 l.ori r6,r0,0x1 // write access
324 l.j 2f
325 l.nop
326 1: l.ori r6,r0,0x0 // !write access
330 l.jal do_page_fault
331 l.nop
332 l.j _ret_from_exception
333 l.nop
338 l.and r5,r5,r0
339 l.j 1f
340 l.nop
345 l.ori r5,r0,0x400 // exception vector
347 l.addi r3,r1,0 // pt_regs
349 l.ori r6,r0,0x0 // !write access
352 l.jal do_page_fault
353 l.nop
354 l.j _ret_from_exception
355 l.nop
362 l.jal timer_interrupt
363 l.addi r3,r1,0 /* pt_regs */
365 l.j _ret_from_intr
366 l.nop
373 l.jal do_unaligned_access
374 l.addi r3,r1,0 /* pt_regs */
376 l.j _ret_from_exception
377 l.nop
381 // l.mfspr r2,r0,SPR_EEAR_BASE /* Load the effective address */
382 l.addi r2,r4,0
383 // l.mfspr r5,r0,SPR_EPCR_BASE /* Load the insn address */
384 l.lwz r5,PT_PC(r1)
386 l.lwz r3,0(r5) /* Load insn */
387 l.srli r4,r3,26 /* Shift left to get the insn opcode */
389 l.sfeqi r4,0x00 /* Check if the load/store insn is in delay slot */
390 l.bf jmp
391 l.sfeqi r4,0x01
392 l.bf jmp
393 l.sfeqi r4,0x03
394 l.bf jmp
395 l.sfeqi r4,0x04
396 l.bf jmp
397 l.sfeqi r4,0x11
398 l.bf jr
399 l.sfeqi r4,0x12
400 l.bf jr
401 l.nop
402 l.j 1f
403 l.addi r5,r5,4 /* Increment PC to get return insn address */
406 l.slli r4,r3,6 /* Get the signed extended jump length */
407 l.srai r4,r4,4
409 l.lwz r3,4(r5) /* Load the real load/store insn */
411 l.add r5,r5,r4 /* Calculate jump target address */
413 l.j 1f
414 l.srli r4,r3,26 /* Shift left to get the insn opcode */
417 l.slli r4,r3,9 /* Shift to get the reg nb */
418 l.andi r4,r4,0x7c
420 l.lwz r3,4(r5) /* Load the real load/store insn */
422 l.add r4,r4,r1 /* Load the jump register value from the stack */
423 l.lwz r5,0(r4)
425 l.srli r4,r3,26 /* Shift left to get the insn opcode */
429 // l.mtspr r0,r5,SPR_EPCR_BASE
430 l.sw PT_PC(r1),r5
432 l.sfeqi r4,0x26
433 l.bf lhs
434 l.sfeqi r4,0x25
435 l.bf lhz
436 l.sfeqi r4,0x22
437 l.bf lws
438 l.sfeqi r4,0x21
439 l.bf lwz
440 l.sfeqi r4,0x37
441 l.bf sh
442 l.sfeqi r4,0x35
443 l.bf sw
444 l.nop
446 1: l.j 1b /* I don't know what to do */
447 l.nop
449 lhs: l.lbs r5,0(r2)
450 l.slli r5,r5,8
451 l.lbz r6,1(r2)
452 l.or r5,r5,r6
453 l.srli r4,r3,19
454 l.andi r4,r4,0x7c
455 l.add r4,r4,r1
456 l.j align_end
457 l.sw 0(r4),r5
459 lhz: l.lbz r5,0(r2)
460 l.slli r5,r5,8
461 l.lbz r6,1(r2)
462 l.or r5,r5,r6
463 l.srli r4,r3,19
464 l.andi r4,r4,0x7c
465 l.add r4,r4,r1
466 l.j align_end
467 l.sw 0(r4),r5
469 lws: l.lbs r5,0(r2)
470 l.slli r5,r5,24
471 l.lbz r6,1(r2)
472 l.slli r6,r6,16
473 l.or r5,r5,r6
474 l.lbz r6,2(r2)
475 l.slli r6,r6,8
476 l.or r5,r5,r6
477 l.lbz r6,3(r2)
478 l.or r5,r5,r6
479 l.srli r4,r3,19
480 l.andi r4,r4,0x7c
481 l.add r4,r4,r1
482 l.j align_end
483 l.sw 0(r4),r5
485 lwz: l.lbz r5,0(r2)
486 l.slli r5,r5,24
487 l.lbz r6,1(r2)
488 l.slli r6,r6,16
489 l.or r5,r5,r6
490 l.lbz r6,2(r2)
491 l.slli r6,r6,8
492 l.or r5,r5,r6
493 l.lbz r6,3(r2)
494 l.or r5,r5,r6
495 l.srli r4,r3,19
496 l.andi r4,r4,0x7c
497 l.add r4,r4,r1
498 l.j align_end
499 l.sw 0(r4),r5
502 l.srli r4,r3,9
503 l.andi r4,r4,0x7c
504 l.add r4,r4,r1
505 l.lwz r5,0(r4)
506 l.sb 1(r2),r5
507 l.srli r5,r5,8
508 l.j align_end
509 l.sb 0(r2),r5
512 l.srli r4,r3,9
513 l.andi r4,r4,0x7c
514 l.add r4,r4,r1
515 l.lwz r5,0(r4)
516 l.sb 3(r2),r5
517 l.srli r5,r5,8
518 l.sb 2(r2),r5
519 l.srli r5,r5,8
520 l.sb 1(r2),r5
521 l.srli r5,r5,8
522 l.j align_end
523 l.sb 0(r2),r5
526 l.j _ret_from_intr
527 l.nop
534 l.jal do_illegal_instruction
535 l.addi r3,r1,0 /* pt_regs */
537 l.j _ret_from_exception
538 l.nop
544 l.lwz r4,PT_SR(r1) // were interrupts enabled ?
545 l.andi r4,r4,SPR_SR_IEE
546 l.sfeqi r4,0
547 l.bnf 1f // ext irq enabled, all ok.
548 l.nop
551 l.addi r1,r1,-0x8
552 l.movhi r3,hi(42f)
553 l.ori r3,r3,lo(42f)
554 l.sw 0x0(r1),r3
555 l.jal _printk
556 l.sw 0x4(r1),r4
557 l.addi r1,r1,0x8
566 l.ori r4,r4,SPR_SR_IEE // fix the bug
567 // l.sw PT_SR(r1),r4
571 l.addi r3,r1,0
572 l.movhi r8,hi(generic_handle_arch_irq)
573 l.ori r8,r8,lo(generic_handle_arch_irq)
574 l.jalr r8
575 l.nop
576 l.j _ret_from_intr
577 l.nop
609 l.sw PT_GPR2(r1),r2
614 l.sw PT_GPR3(r1),r3
621 l.lwz r4,PT_GPR4(r1)
622 l.sw PT_GPR5(r1),r5
623 l.sw PT_GPR6(r1),r6
624 l.sw PT_GPR7(r1),r7
625 l.sw PT_GPR8(r1),r8
626 l.sw PT_GPR9(r1),r9
628 l.sw PT_GPR11(r1),r11
630 l.sw PT_ORIG_GPR11(r1),r11
642 /* l.sw PT_GPR30(r1),r30 */
650 l.lwz r30,TI_FLAGS(r10)
651 l.andi r30,r30,_TIF_SYSCALL_TRACE
652 l.sfne r30,r0
653 l.bf _syscall_trace_enter
654 l.nop
658 l.sfgeui r11,__NR_syscalls
659 l.bf _syscall_badsys
660 l.nop
663 l.movhi r29,hi(sys_call_table)
664 l.ori r29,r29,lo(sys_call_table)
665 l.slli r11,r11,2
666 l.add r29,r29,r11
667 l.lwz r29,0(r29)
669 l.jalr r29
670 l.nop
676 l.sw PT_GPR11(r1),r11 // save return value
680 l.movhi r3,hi(_string_syscall_return)
681 l.ori r3,r3,lo(_string_syscall_return)
682 l.ori r27,r0,2
683 l.sw -4(r1),r27
684 l.sw -8(r1),r11
685 l.lwz r29,PT_ORIG_GPR11(r1)
686 l.sw -12(r1),r29
687 l.lwz r29,PT_GPR9(r1)
688 l.sw -16(r1),r29
689 l.movhi r27,hi(_printk)
690 l.ori r27,r27,lo(_printk)
691 l.jalr r27
692 l.addi r1,r1,-16
693 l.addi r1,r1,16
697 l.movhi r27,hi(show_registers)
698 l.ori r27,r27,lo(show_registers)
699 l.jalr r27
700 l.or r3,r1,r1
708 l.sfne r30,r0
709 l.bf _syscall_trace_leave
710 l.nop
718 l.jal rseq_syscall
719 l.ori r3,r1,0
724 l.lwz r30,TI_FLAGS(r10)
725 l.andi r30,r30,_TIF_WORK_MASK
726 l.sfne r30,r0
728 l.bnf _syscall_resume_userspace
729 l.nop
735 l.sw PT_GPR14(r1),r14
736 l.sw PT_GPR16(r1),r16
737 l.sw PT_GPR18(r1),r18
738 l.sw PT_GPR20(r1),r20
739 l.sw PT_GPR22(r1),r22
740 l.sw PT_GPR24(r1),r24
741 l.sw PT_GPR26(r1),r26
742 l.sw PT_GPR28(r1),r28
745 l.j _work_pending
746 l.nop
772 l.lwz r2,PT_GPR2(r1)
778 l.lwz r3,PT_GPR3(r1)
779 l.lwz r4,PT_GPR4(r1)
780 l.lwz r5,PT_GPR5(r1)
781 l.lwz r6,PT_GPR6(r1)
782 l.lwz r7,PT_GPR7(r1)
783 l.lwz r8,PT_GPR8(r1)
785 l.lwz r9,PT_GPR9(r1)
786 l.lwz r10,PT_GPR10(r1)
787 l.lwz r11,PT_GPR11(r1)
790 l.lwz r30,PT_GPR30(r1)
793 l.lwz r13,PT_PC(r1)
794 l.lwz r15,PT_SR(r1)
795 l.lwz r1,PT_SP(r1)
798 * them before we can use them for our l.rfe */
800 l.mtspr r0,r13,SPR_EPCR_BASE
801 l.mtspr r0,r15,SPR_ESR_BASE
802 l.rfe
816 l.jal do_syscall_trace_enter
817 l.addi r3,r1,0
823 l.lwz r11,PT_GPR11(r1)
824 l.lwz r3,PT_GPR3(r1)
825 l.lwz r4,PT_GPR4(r1)
826 l.lwz r5,PT_GPR5(r1)
827 l.lwz r6,PT_GPR6(r1)
828 l.lwz r7,PT_GPR7(r1)
830 l.j _syscall_check
831 l.lwz r8,PT_GPR8(r1)
834 l.jal do_syscall_trace_leave
835 l.addi r3,r1,0
837 l.j _syscall_check_work
838 l.nop
846 l.j _syscall_return
847 l.addi r11,r0,-ENOSYS
857 l.jal do_fpe_trap
858 l.addi r3,r1,0 /* pt_regs */
860 l.j _ret_from_exception
861 l.nop
868 l.jal do_trap
869 l.addi r3,r1,0 /* pt_regs */
871 l.j _ret_from_exception
872 l.nop
947 l.lwz r4,TI_FLAGS(r10)
948 l.andi r13,r4,_TIF_WORK_MASK
949 l.sfeqi r13,0
950 l.bf _restore_all
951 l.nop
954 l.lwz r5,PT_ORIG_GPR11(r1)
955 l.sfltsi r5,0
956 l.bnf 1f
957 l.nop
958 l.andi r5,r5,0
960 l.jal do_work_pending
961 l.ori r3,r1,0 /* pt_regs */
963 l.sfeqi r11,0
964 l.bf _restore_all
965 l.nop
966 l.sfltsi r11,0
967 l.bnf 1f
968 l.nop
969 l.and r11,r11,r0
970 l.ori r11,r11,__NR_restart_syscall
971 l.j _syscall_check_trace_enter
972 l.nop
974 l.lwz r11,PT_ORIG_GPR11(r1)
976 l.lwz r3,PT_GPR3(r1)
977 l.lwz r4,PT_GPR4(r1)
978 l.lwz r5,PT_GPR5(r1)
979 l.lwz r6,PT_GPR6(r1)
980 l.lwz r7,PT_GPR7(r1)
981 l.j _syscall_check_trace_enter
982 l.lwz r8,PT_GPR8(r1)
986 l.lwz r4,PT_SR(r1)
987 l.andi r3,r4,(SPR_SR_IEE|SPR_SR_TEE)
988 l.sfeq r3,r0 /* skip trace if irqs were off */
989 l.bf skip_hardirqs_on
990 l.nop
1000 l.lwz r4,PT_SR(r1)
1001 l.andi r3,r4,SPR_SR_SM
1002 l.sfeqi r3,0
1003 l.bnf _restore_all
1004 l.nop
1005 l.j _resume_userspace
1006 l.nop
1009 l.jal schedule_tail
1010 l.nop
1013 l.sfeqi r20,0
1014 l.bf 1f
1015 l.nop
1018 l.jalr r20
1019 l.or r3,r22,r0
1023 l.lwz r11,PT_GPR11(r1)
1030 l.lwz r14,PT_GPR14(r1)
1031 l.lwz r16,PT_GPR16(r1)
1032 l.lwz r18,PT_GPR18(r1)
1033 l.lwz r20,PT_GPR20(r1)
1034 l.lwz r22,PT_GPR22(r1)
1035 l.lwz r24,PT_GPR24(r1)
1036 l.lwz r26,PT_GPR26(r1)
1037 l.lwz r28,PT_GPR28(r1)
1039 l.j _syscall_return
1040 l.nop
1066 * the l.rfe instruction. If get TLB miss in beetwen the EPCR register gets
1067 * garbled and we end up calling l.rfe with the wrong EPCR. (same probably
1087 l.addi r1,r1,-(INT_FRAME_SIZE)
1090 l.sw PT_GPR2(r1),r2
1091 l.sw PT_GPR9(r1),r9
1094 l.sw PT_GPR14(r1),r14
1095 l.sw PT_GPR16(r1),r16
1096 l.sw PT_GPR18(r1),r18
1097 l.sw PT_GPR20(r1),r20
1098 l.sw PT_GPR22(r1),r22
1099 l.sw PT_GPR24(r1),r24
1100 l.sw PT_GPR26(r1),r26
1101 l.sw PT_GPR28(r1),r28
1102 l.sw PT_GPR30(r1),r30
1104 l.addi r11,r10,0 /* Save old 'current' to 'last' return value*/
1114 l.lwz r29,TI_KSP(r10)
1115 l.sw PT_SP(r1),r29
1118 l.sw TI_KSP(r10),r1 /* Save old stack pointer */
1119 l.or r10,r4,r0 /* Set up new current_thread_info */
1120 l.lwz r1,TI_KSP(r10) /* Load new stack pointer */
1123 l.lwz r29,PT_SP(r1)
1124 l.sw TI_KSP(r10),r29
1129 l.lwz r2,PT_GPR2(r1)
1130 l.lwz r9,PT_GPR9(r1)
1135 l.lwz r14,PT_GPR14(r1)
1136 l.lwz r16,PT_GPR16(r1)
1137 l.lwz r18,PT_GPR18(r1)
1138 l.lwz r20,PT_GPR20(r1)
1139 l.lwz r22,PT_GPR22(r1)
1140 l.lwz r24,PT_GPR24(r1)
1141 l.lwz r26,PT_GPR26(r1)
1142 l.lwz r28,PT_GPR28(r1)
1143 l.lwz r30,PT_GPR30(r1)
1146 l.addi r1,r1,(INT_FRAME_SIZE)
1154 l.lwz r3,TI_TASK(r3) /* Load 'prev' as schedule_tail arg */
1155 l.jr r9
1156 l.nop
1161 * jump is always happening after the l.addi instruction.
1165 * code that did the l.jal that brought us here.
1175 l.sw PT_GPR14(r1),r14
1176 l.sw PT_GPR16(r1),r16
1177 l.sw PT_GPR18(r1),r18
1178 l.sw PT_GPR20(r1),r20
1179 l.sw PT_GPR22(r1),r22
1180 l.sw PT_GPR24(r1),r24
1181 l.sw PT_GPR26(r1),r26
1182 l.jr r29
1183 l.sw PT_GPR28(r1),r28
1186 l.movhi r29,hi(sys_clone)
1187 l.j _fork_save_extra_regs_and_call
1188 l.ori r29,r29,lo(sys_clone)
1191 l.movhi r29,hi(sys_clone3)
1192 l.j _fork_save_extra_regs_and_call
1193 l.ori r29,r29,lo(sys_clone3)
1196 l.movhi r29,hi(sys_fork)
1197 l.j _fork_save_extra_regs_and_call
1198 l.ori r29,r29,lo(sys_fork)
1201 l.jal _sys_rt_sigreturn
1202 l.addi r3,r1,0
1203 l.sfne r30,r0
1204 l.bnf _no_syscall_trace
1205 l.nop
1206 l.jal do_syscall_trace_leave
1207 l.addi r3,r1,0
1209 l.j _resume_userspace
1210 l.nop
1229 l.lwz r29,0(r4)
1230 l.lwz r27,0(r5)
1231 l.sw 0(r4),r27
1232 l.sw 0(r5),r29
1234 l.jr r9
1235 l.or r11,r0,r0