1 // SPDX-License-Identifier: GPL-2.0-or-later
27 #define M41T81REG_SC_ST		0x80		/* stop bit */
28 #define M41T81REG_HR_CB		0x40		/* century bit */
29 #define M41T81REG_HR_CEB	0x80		/* century enable bit */
30 #define M41T81REG_CTL_S		0x20		/* sign bit */
31 #define M41T81REG_CTL_FT	0x40		/* frequency test bit */
32 #define M41T81REG_CTL_OUT	0x80		/* output level */
33 #define M41T81REG_WD_RB0	0x01		/* watchdog resolution bit 0 */
34 #define M41T81REG_WD_RB1	0x02		/* watchdog resolution bit 1 */
35 #define M41T81REG_WD_BMB0	0x04		/* watchdog multiplier bit 0 */
36 #define M41T81REG_WD_BMB1	0x08		/* watchdog multiplier bit 1 */
37 #define M41T81REG_WD_BMB2	0x10		/* watchdog multiplier bit 2 */
38 #define M41T81REG_WD_BMB3	0x20		/* watchdog multiplier bit 3 */
39 #define M41T81REG_WD_BMB4	0x40		/* watchdog multiplier bit 4 */
40 #define M41T81REG_AMO_ABE	0x20		/* alarm in "battery back-up mode" enable bit */
41 #define M41T81REG_AMO_SQWE	0x40		/* square wave enable */
42 #define M41T81REG_AMO_AFE	0x80		/* alarm flag enable flag */
43 #define M41T81REG_ADT_RPT5	0x40		/* alarm repeat mode bit 5 */
44 #define M41T81REG_ADT_RPT4	0x80		/* alarm repeat mode bit 4 */
45 #define M41T81REG_AHR_RPT3	0x80		/* alarm repeat mode bit 3 */
46 #define M41T81REG_AHR_HT	0x40		/* halt update bit */
47 #define M41T81REG_AMN_RPT2	0x80		/* alarm repeat mode bit 2 */
48 #define M41T81REG_ASC_RPT1	0x80		/* alarm repeat mode bit 1 */
49 #define M41T81REG_FLG_AF	0x40		/* alarm flag (read only) */
50 #define M41T81REG_FLG_WDF	0x80		/* watchdog flag (read only) */
51 #define M41T81REG_SQW_RS0	0x10		/* sqw frequency bit 0 */
52 #define M41T81REG_SQW_RS1	0x20		/* sqw frequency bit 1 */
53 #define M41T81REG_SQW_RS2	0x40		/* sqw frequency bit 2 */
54 #define M41T81REG_SQW_RS3	0x80		/* sqw frequency bit 3 */
61 #define M41T81REG_TSC	0x00		/* tenths/hundredths of second */
62 #define M41T81REG_SC	0x01		/* seconds */
63 #define M41T81REG_MN	0x02		/* minute */
64 #define M41T81REG_HR	0x03		/* hour/century */
65 #define M41T81REG_DY	0x04		/* day of week */
66 #define M41T81REG_DT	0x05		/* date of month */
67 #define M41T81REG_MO	0x06		/* month */
68 #define M41T81REG_YR	0x07		/* year */
69 #define M41T81REG_CTL	0x08		/* control */
70 #define M41T81REG_WD	0x09		/* watchdog */
71 #define M41T81REG_AMO	0x0A		/* alarm: month */
72 #define M41T81REG_ADT	0x0B		/* alarm: date */
73 #define M41T81REG_AHR	0x0C		/* alarm: hour */
74 #define M41T81REG_AMN	0x0D		/* alarm: minute */
75 #define M41T81REG_ASC	0x0E		/* alarm: second */
76 #define M41T81REG_FLG	0x0F		/* flags */
77 #define M41T81REG_SQW	0x13		/* square wave register */
79 #define M41T81_CCR_ADDRESS	0x68
88 	__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));  in m41t81_read()
104 		return -1;  in m41t81_read()
107 	return __raw_readq(SMB_CSR(R_SMB_DATA)) & 0xff;  in m41t81_read()
115 	__raw_writeq(addr & 0xff, SMB_CSR(R_SMB_CMD));  in m41t81_write()
116 	__raw_writeq(b & 0xff, SMB_CSR(R_SMB_DATA));  in m41t81_write()
126 		return -1;  in m41t81_write()
136 	return 0;  in m41t81_write()
161 	tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0);  in m41t81_set_time()
164 	/* tm_wday starts from 0 to 6 */  in m41t81_set_time()
165 	if (tm.tm_wday == 0) tm.tm_wday = 7;  in m41t81_set_time()
172 	/* tm_mon starts from 0, *ick* */  in m41t81_set_time()
183 	return 0;  in m41t81_set_time()
188 	unsigned int year, mon, day, hour, min, sec;  in m41t81_get_time()  local
201 	hour = m41t81_read(M41T81REG_HR) & 0x3f;  in m41t81_get_time()
203 	mon = m41t81_read(M41T81REG_MO);  in m41t81_get_time()
211 	mon = bcd2bin(mon);  in m41t81_get_time()
216 	return mktime64(year, mon, day, hour, min, sec);  in m41t81_get_time()
225 	m41t81_write(M41T81REG_SC, tmp & 0x7f);  in m41t81_probe()
227 	return m41t81_read(M41T81REG_SC) != -1;  in m41t81_probe()