Lines Matching +full:gfx +full:- +full:mem
22 #define SGIMC_CCTRL0_EPERRMEM 0x00000040 /* Main mem parity error enable */
32 #define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
33 #define SGIMC_CCTRL0_LENDIAN 0x00020000 /* Put MC in little-endian mode */
34 #define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
35 #define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
36 #define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
64 #define SGIMC_EEPROM_SDATAO 0x00000008 /* Serial EEPROM data-out */
65 #define SGIMC_EEPROM_SDATAI 0x00000010 /* Serial EEPROM data-in */
75 #define SGIMC_GIOPAR_HPC64 0x00000001 /* HPC talks to GIO using 64-bits */
76 #define SGIMC_GIOPAR_GFX64 0x00000002 /* GFX talks to GIO using 64-bits */
77 #define SGIMC_GIOPAR_EXP064 0x00000004 /* EXP(slot0) talks using 64-bits */
78 #define SGIMC_GIOPAR_EXP164 0x00000008 /* EXP(slot1) talks using 64-bits */
79 #define SGIMC_GIOPAR_EISA64 0x00000010 /* EISA bus talks 64-bits to GIO */
80 #define SGIMC_GIOPAR_HPC264 0x00000020 /* 2nd HPX talks 64-bits to GIO */
81 #define SGIMC_GIOPAR_RTIMEGFX 0x00000040 /* GFX device has realtime attr */
86 #define SGIMC_GIOPAR_MASTERGFX 0x00000800 /* GFX can act as a bus master */
110 volatile u32 cmacc; /* Mem access config for CPU */
112 volatile u32 gmacc; /* Mem access config for GIO */
146 volatile u32 syssembit; /* Uni-bit system semaphore */
191 u32 _unused36[0x1000/4-2*4];