Lines Matching +full:1 +full:- +full:bit +full:- +full:only
7 * Copyright (c) 2003-2008 Cavium Networks
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
50 CVMX_FAU_OP_SIZE_16 = 1,
57 * bit will be set. Otherwise the value of the register before
61 uint64_t error:1;
67 * bit will be set. Otherwise the value of the register before
71 uint64_t error:1;
77 * bit will be set. Otherwise the value of the register before
81 uint64_t error:1;
87 * bit will be set. Otherwise the value of the register before
91 uint64_t error:1;
97 * the error bit will be set. Otherwise the value of the
103 uint64_t invalid:1;
122 * 1 = Store value is atomically written over the current value
124 * - Step by 2 for 16 bit access.
125 * - Step by 4 for 32 bit access.
126 * - Step by 8 for 64 bit access.
141 * - 0 = Don't wait
142 * - 1 = Wait for tag switch to complete
144 * - Step by 2 for 16 bit access.
145 * - Step by 4 for 32 bit access.
146 * - Step by 8 for 64 bit access.
148 * Note: When performing 32 and 64 bit access, only the low
162 * Perform an atomic 64 bit add
165 * - Step by 8 for 64 bit access.
167 * Note: Only the low 22 bits are available.
177 * Perform an atomic 32 bit add
180 * - Step by 4 for 32 bit access.
182 * Note: Only the low 22 bits are available.
193 * Perform an atomic 16 bit add
196 * - Step by 2 for 16 bit access.
208 * Perform an atomic 8 bit add
221 * Perform an atomic 64 bit add after the current tag switch
225 * - Step by 8 for 64 bit access.
227 * Note: Only the low 22 bits are available.
228 * Returns If a timeout occurs, the error bit will be set. Otherwise
240 cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); in cvmx_fau_tagwait_fetch_and_add64()
245 * Perform an atomic 32 bit add after the current tag switch
249 * - Step by 4 for 32 bit access.
251 * Note: Only the low 22 bits are available.
252 * Returns If a timeout occurs, the error bit will be set. Otherwise
265 cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); in cvmx_fau_tagwait_fetch_and_add32()
270 * Perform an atomic 16 bit add after the current tag switch
274 * - Step by 2 for 16 bit access.
276 * Returns If a timeout occurs, the error bit will be set. Otherwise
289 cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); in cvmx_fau_tagwait_fetch_and_add16()
294 * Perform an atomic 8 bit add after the current tag switch
299 * Returns If a timeout occurs, the error bit will be set. Otherwise
311 result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); in cvmx_fau_tagwait_fetch_and_add8()
320 * Note: When performing 32 and 64 bit access, only the low
324 * - 0 = Don't wait
325 * - 1 = Wait for tag switch to complete
327 * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits
328 * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits
329 * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits
330 * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits
332 * - Step by 2 for 16 bit access.
333 * - Step by 4 for 32 bit access.
334 * - Step by 8 for 64 bit access.
344 cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | in __cvmx_fau_iobdma_data()
352 * Perform an async atomic 64 bit add. The old value is
358 * - Step by 8 for 64 bit access.
360 * Note: Only the low 22 bits are available.
372 * Perform an async atomic 32 bit add. The old value is
378 * - Step by 4 for 32 bit access.
380 * Note: Only the low 22 bits are available.
392 * Perform an async atomic 16 bit add. The old value is
398 * - Step by 2 for 16 bit access.
411 * Perform an async atomic 8 bit add. The old value is
429 * Perform an async atomic 64 bit add after the current tag
433 * 8 byte aligned. If a timeout occurs, the error bit (63)
438 * - Step by 8 for 64 bit access.
440 * Note: Only the low 22 bits are available.
448 (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); in cvmx_fau_async_tagwait_fetch_and_add64()
452 * Perform an async atomic 32 bit add after the current tag
456 * 8 byte aligned. If a timeout occurs, the error bit (63)
461 * - Step by 4 for 32 bit access.
463 * Note: Only the low 22 bits are available.
471 (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); in cvmx_fau_async_tagwait_fetch_and_add32()
475 * Perform an async atomic 16 bit add after the current tag
479 * 8 byte aligned. If a timeout occurs, the error bit (63)
484 * - Step by 2 for 16 bit access.
494 (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); in cvmx_fau_async_tagwait_fetch_and_add16()
498 * Perform an async atomic 8 bit add after the current tag
502 * 8 byte aligned. If a timeout occurs, the error bit (63)
516 (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); in cvmx_fau_async_tagwait_fetch_and_add8()
520 * Perform an atomic 64 bit add
523 * - Step by 8 for 64 bit access.
532 * Perform an atomic 32 bit add
535 * - Step by 4 for 32 bit access.
545 * Perform an atomic 16 bit add
548 * - Step by 2 for 16 bit access.
558 * Perform an atomic 8 bit add
570 * Perform an atomic 64 bit write
573 * - Step by 8 for 64 bit access.
578 cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); in cvmx_fau_atomic_write64()
582 * Perform an atomic 32 bit write
585 * - Step by 4 for 32 bit access.
591 cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); in cvmx_fau_atomic_write32()
595 * Perform an atomic 16 bit write
598 * - Step by 2 for 16 bit access.
604 cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); in cvmx_fau_atomic_write16()
608 * Perform an atomic 8 bit write
616 cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); in cvmx_fau_atomic_write8()