Lines Matching +full:target +full:- +full:5 +full:v +full:- +full:supply
6 * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
38 /* Au1000-style (IC0/1): 2 controllers with 32 sources each */
45 /* Au1300-style (GPIC): 1 controller with up to 128 sources */
48 #define ALCHEMY_GPIC_INT_LAST (ALCHEMY_GPIC_INT_BASE + ALCHEMY_GPIC_INT_NUM - 1)
105 * 0..au1000 1..au1500 2..au1100 3..au1550 4..au1200 5..au1300
109 #define AU1300_ROM_PHYS_ADDR 0x10000000 /* 5 */
110 #define AU1300_OTP_PHYS_ADDR 0x10002000 /* 5 */
111 #define AU1300_VSS_PHYS_ADDR 0x10003000 /* 5 */
112 #define AU1300_UART0_PHYS_ADDR 0x10100000 /* 5 */
113 #define AU1300_UART1_PHYS_ADDR 0x10101000 /* 5 */
114 #define AU1300_UART2_PHYS_ADDR 0x10102000 /* 5 */
115 #define AU1300_UART3_PHYS_ADDR 0x10103000 /* 5 */
118 #define AU1300_GPIC_PHYS_ADDR 0x10200000 /* 5 */
122 #define AU1300_GPU_PHYS_ADDR 0x10500000 /* 5 */
127 #define AU1300_SD1_PHYS_ADDR 0x10601000 /* 5 */
128 #define AU1300_SD2_PHYS_ADDR 0x10602000 /* 5 */
130 #define AU1300_SYS_PHYS_ADDR 0x10900000 /* 5 */
133 #define AU1300_PSC0_PHYS_ADDR 0x10A00000 /* 5 */
134 #define AU1300_PSC1_PHYS_ADDR 0x10A01000 /* 5 */
135 #define AU1300_PSC2_PHYS_ADDR 0x10A02000 /* 5 */
136 #define AU1300_PSC3_PHYS_ADDR 0x10A03000 /* 5 */
155 #define AU1300_UDMA_PHYS_ADDR 0x14001800 /* 5 */
166 #define AU1300_MAEITE_PHYS_ADDR 0x14010000 /* 5 */
167 #define AU1300_MAEMPE_PHYS_ADDR 0x14014000 /* 5 */
174 #define AU1300_USB_EHCI_PHYS_ADDR 0x14020000 /* 5 */
175 #define AU1300_USB_OHCI0_PHYS_ADDR 0x14020400 /* 5 */
176 #define AU1300_USB_OHCI1_PHYS_ADDR 0x14020800 /* 5 */
177 #define AU1300_USB_CTL_PHYS_ADDR 0x14021000 /* 5 */
178 #define AU1300_USB_OTG_PHYS_ADDR 0x14022000 /* 5 */
179 #define AU1300_MAEBSA_PHYS_ADDR 0x14030000 /* 5 */
214 (((gpio) >> 5) * 4)
231 #define GPIC_CFG_IC_EDGE_FALL (5 << 4)
266 #define MEM_SDMODE_TRP (3 << 5)
285 #define MEM_SDMODE_TRP_N(N) ((N) << 5)
363 # define SYS_CNTRL_32S (1 << 5)
399 # define SYS_PF_I2S (1 << 5) /* I2S/GPIO[29:31] */
426 # define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
452 #define SYS_PINFUNC_S0C (1 << 5)
537 #define PCI_CONFIG_ET (1 << 26) /* error in target mode */
544 #define PCI_CONFIG_NC (1 << 16) /* mark mem access non-coherent */
545 #define PCI_CONFIG_IA (1 << 15) /* INTA# enabled (target mode) */
549 #define PCI_CONFIG_ITM (1 << 10) /* int on target abort (as master) */
550 #define PCI_CONFIG_ITT (1 << 9) /* int on target abort (as target) */
556 #define PCI_CONFIG_ST (1 << 5) /* swap data by target transactions */
559 #define PCI_CONFIG_R2H (1 << 2) /* REQ2# to hi-prio arbiter */
560 #define PCI_CONFIG_R1H (1 << 1) /* REQ1# to hi-prio arbiter */
561 #define PCI_CONFIG_CH (1 << 0) /* PCI ctl to hi-prio arbiter */
584 #define PCI_TIMEOUT_TO(x) ((x) & 0xff) /* target ready timeout */
611 static inline void alchemy_wrsys(unsigned long v, int regofs) in alchemy_wrsys() argument
615 __raw_writel(v, b + regofs); in alchemy_wrsys()
627 static inline void alchemy_wrsmem(unsigned long v, int regofs) in alchemy_wrsmem() argument
631 __raw_writel(v, b + regofs); in alchemy_wrsmem()
635 /* Early Au1000 have a write-only SYS_CPUPLL register. */
652 * early revisions of Alchemy SOCs. It disables the bus trans- in au1xxx_cpu_needs_config_od()
674 #define ALCHEMY_CPU_UNKNOWN -1
680 #define ALCHEMY_CPU_AU1300 5
761 for (i = 10000; i; i--) in alchemy_uart_putchar()
763 } while (--timeout); in alchemy_uart_putchar()
823 * GPIO controller or a on-chip peripheral.
828 /* wake-from-str pins 0-3 */
831 /* external clock sources for PSCs: 4-5 */
833 /* 8bit MMC interface on SD0: 6-9 */
838 /* UART1 pins: 11-18 */
842 /* UART0 pins: 19-24 */
845 /* UART2: 25-26 */
847 /* UART3: 27-28 */
849 /* LCD controller PWMs, ext pixclock: 29-31 */
851 /* SD1 interface: 32-37 */
854 /* SD2 interface: 38-43 */
857 /* PSC0/1 clocks: 44-45 */
859 /* PSCs: 46-49/50-53/54-57/58-61 */
868 /* PCMCIA interface: 62-70 */
872 /* camera interface H/V sync inputs: 71-72 */
874 /* PSC2/3 clocks: 73-74 */
884 /* Au1300 allows to disconnect certain blocks from internal power supply */