Lines Matching +full:0 +full:- +full:7
1 // SPDX-License-Identifier: GPL-2.0
5 compatible = "simple-bus";
6 #address-cells = <2>;
7 #size-cells = <2>;
8 ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* PIO & CONF & APB */
9 0 0x20000000 0 0x20000000 0 0x10000000
10 0 0x40000000 0 0x40000000 0 0x40000000 /* PCI MEM */
11 0xe00 0x00000000 0xe00 0x00000000 0x100 0x0000000>;
13 pic: interrupt-controller@10000000 {
14 compatible = "loongson,pch-pic-1.0";
15 reg = <0 0x10000000 0 0x400>;
16 interrupt-controller;
17 interrupt-parent = <&htvec>;
18 loongson,pic-base-vec = <0>;
19 #interrupt-cells = <2>;
23 compatible = "loongson,ls7a-rtc";
24 reg = <0 0x100d0100 0 0x78>;
25 interrupt-parent = <&pic>;
31 reg = <0 0x10080000 0 0x100>;
32 clock-frequency = <50000000>;
33 interrupt-parent = <&pic>;
35 no-loopback-test;
41 reg = <0 0x10080100 0 0x100>;
42 clock-frequency = <50000000>;
43 interrupt-parent = <&pic>;
45 no-loopback-test;
51 reg = <0 0x10080200 0 0x100>;
52 clock-frequency = <50000000>;
53 interrupt-parent = <&pic>;
55 no-loopback-test;
61 reg = <0 0x10080300 0 0x100>;
62 clock-frequency = <50000000>;
63 interrupt-parent = <&pic>;
65 no-loopback-test;
69 compatible = "loongson,ls7a-pci";
71 #address-cells = <3>;
72 #size-cells = <2>;
73 msi-parent = <&msi>;
75 reg = <0 0x1a000000 0 0x02000000>,
76 <0xefe 0x00000000 0 0x20000000>;
78 ranges = <0x01000000 0x0 0x00020000 0x0 0x18020000 0x0 0x00020000>,
79 <0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
81 ohci@4,0 {
82 compatible = "pci0014,7a24.0",
83 "pci0014,7a24",
87 reg = <0x2000 0x0 0x0 0x0 0x0>;
89 interrupt-parent = <&pic>;
93 compatible = "pci0014,7a14.0",
94 "pci0014,7a14",
98 reg = <0x2100 0x0 0x0 0x0 0x0>;
100 interrupt-parent = <&pic>;
103 ohci@5,0 {
104 compatible = "pci0014,7a24.0",
105 "pci0014,7a24",
109 reg = <0x2800 0x0 0x0 0x0 0x0>;
111 interrupt-parent = <&pic>;
115 compatible = "pci0014,7a14.0",
116 "pci0014,7a14",
120 reg = <0x2900 0x0 0x0 0x0 0x0>;
122 interrupt-parent = <&pic>;
125 sata@8,0 {
126 compatible = "pci0014,7a08.0",
127 "pci0014,7a08",
131 reg = <0x4000 0x0 0x0 0x0 0x0>;
133 interrupt-parent = <&pic>;
137 compatible = "pci0014,7a08.0",
138 "pci0014,7a08",
142 reg = <0x4100 0x0 0x0 0x0 0x0>;
144 interrupt-parent = <&pic>;
148 compatible = "pci0014,7a08.0",
149 "pci0014,7a08",
153 reg = <0x4200 0x0 0x0 0x0 0x0>;
155 interrupt-parent = <&pic>;
158 gpu@6,0 {
159 compatible = "pci0014,7a15.0",
160 "pci0014,7a15",
164 reg = <0x3000 0x0 0x0 0x0 0x0>;
166 interrupt-parent = <&pic>;
170 compatible = "pci0014,7a06.0",
171 "pci0014,7a06",
175 reg = <0x3100 0x0 0x0 0x0 0x0>;
177 interrupt-parent = <&pic>;
180 hda@7,0 {
181 compatible = "pci0014,7a07.0",
182 "pci0014,7a07",
186 reg = <0x3800 0x0 0x0 0x0 0x0>;
188 interrupt-parent = <&pic>;
191 gmac@3,0 {
192 compatible = "pci0014,7a03.0",
193 "pci0014,7a03",
197 reg = <0x1800 0x0 0x0 0x0 0x0>;
200 interrupt-names = "macirq", "eth_lpi";
201 interrupt-parent = <&pic>;
202 phy-mode = "rgmii";
204 #address-cells = <1>;
205 #size-cells = <0>;
206 compatible = "snps,dwmac-mdio";
207 phy0: ethernet-phy@0 {
208 reg = <0>;
214 compatible = "pci0014,7a03.0",
215 "pci0014,7a03",
218 "loongson, pci-gmac";
220 reg = <0x1900 0x0 0x0 0x0 0x0>;
223 interrupt-names = "macirq", "eth_lpi";
224 interrupt-parent = <&pic>;
225 phy-mode = "rgmii";
227 #address-cells = <1>;
228 #size-cells = <0>;
229 compatible = "snps,dwmac-mdio";
230 phy1: ethernet-phy@1 {
231 reg = <0>;
236 pcie@9,0 {
237 compatible = "pci0014,7a19.1",
238 "pci0014,7a19",
242 reg = <0x4800 0x0 0x0 0x0 0x0>;
244 interrupt-parent = <&pic>;
246 #address-cells = <3>;
247 #size-cells = <2>;
249 #interrupt-cells = <1>;
250 interrupt-map-mask = <0 0 0 0>;
251 interrupt-map = <0 0 0 0 &pic 32 IRQ_TYPE_LEVEL_HIGH>;
255 pcie@a,0 {
256 compatible = "pci0014,7a09.1",
257 "pci0014,7a09",
261 reg = <0x5000 0x0 0x0 0x0 0x0>;
263 interrupt-parent = <&pic>;
265 #address-cells = <3>;
266 #size-cells = <2>;
268 #interrupt-cells = <1>;
269 interrupt-map-mask = <0 0 0 0>;
270 interrupt-map = <0 0 0 0 &pic 33 IRQ_TYPE_LEVEL_HIGH>;
274 pcie@b,0 {
275 compatible = "pci0014,7a09.1",
276 "pci0014,7a09",
280 reg = <0x5800 0x0 0x0 0x0 0x0>;
282 interrupt-parent = <&pic>;
284 #address-cells = <3>;
285 #size-cells = <2>;
287 #interrupt-cells = <1>;
288 interrupt-map-mask = <0 0 0 0>;
289 interrupt-map = <0 0 0 0 &pic 34 IRQ_TYPE_LEVEL_HIGH>;
293 pcie@c,0 {
294 compatible = "pci0014,7a09.1",
295 "pci0014,7a09",
299 reg = <0x6000 0x0 0x0 0x0 0x0>;
301 interrupt-parent = <&pic>;
303 #address-cells = <3>;
304 #size-cells = <2>;
306 #interrupt-cells = <1>;
307 interrupt-map-mask = <0 0 0 0>;
308 interrupt-map = <0 0 0 0 &pic 35 IRQ_TYPE_LEVEL_HIGH>;
312 pcie@d,0 {
313 compatible = "pci0014,7a19.1",
314 "pci0014,7a19",
318 reg = <0x6800 0x0 0x0 0x0 0x0>;
320 interrupt-parent = <&pic>;
322 #address-cells = <3>;
323 #size-cells = <2>;
325 #interrupt-cells = <1>;
326 interrupt-map-mask = <0 0 0 0>;
327 interrupt-map = <0 0 0 0 &pic 36 IRQ_TYPE_LEVEL_HIGH>;
331 pcie@e,0 {
332 compatible = "pci0014,7a09.1",
333 "pci0014,7a09",
337 reg = <0x7000 0x0 0x0 0x0 0x0>;
339 interrupt-parent = <&pic>;
341 #address-cells = <3>;
342 #size-cells = <2>;
344 #interrupt-cells = <1>;
345 interrupt-map-mask = <0 0 0 0>;
346 interrupt-map = <0 0 0 0 &pic 37 IRQ_TYPE_LEVEL_HIGH>;
350 pcie@f,0 {
351 compatible = "pci0014,7a29.1",
352 "pci0014,7a29",
356 reg = <0x7800 0x0 0x0 0x0 0x0>;
358 interrupt-parent = <&pic>;
360 #address-cells = <3>;
361 #size-cells = <2>;
363 #interrupt-cells = <1>;
364 interrupt-map-mask = <0 0 0 0>;
365 interrupt-map = <0 0 0 0 &pic 40 IRQ_TYPE_LEVEL_HIGH>;
369 pcie@10,0 {
370 compatible = "pci0014,7a19.1",
371 "pci0014,7a19",
375 reg = <0x8000 0x0 0x0 0x0 0x0>;
377 interrupt-parent = <&pic>;
379 #address-cells = <3>;
380 #size-cells = <2>;
382 #interrupt-cells = <1>;
383 interrupt-map-mask = <0 0 0 0>;
384 interrupt-map = <0 0 0 0 &pic 41 IRQ_TYPE_LEVEL_HIGH>;
388 pcie@11,0 {
389 compatible = "pci0014,7a29.1",
390 "pci0014,7a29",
394 reg = <0x8800 0x0 0x0 0x0 0x0>;
396 interrupt-parent = <&pic>;
398 #address-cells = <3>;
399 #size-cells = <2>;
401 #interrupt-cells = <1>;
402 interrupt-map-mask = <0 0 0 0>;
403 interrupt-map = <0 0 0 0 &pic 42 IRQ_TYPE_LEVEL_HIGH>;
407 pcie@12,0 {
408 compatible = "pci0014,7a19.1",
409 "pci0014,7a19",
413 reg = <0x9000 0x0 0x0 0x0 0x0>;
415 interrupt-parent = <&pic>;
417 #address-cells = <3>;
418 #size-cells = <2>;
420 #interrupt-cells = <1>;
421 interrupt-map-mask = <0 0 0 0>;
422 interrupt-map = <0 0 0 0 &pic 43 IRQ_TYPE_LEVEL_HIGH>;
426 pcie@13,0 {
427 compatible = "pci0014,7a29.1",
428 "pci0014,7a29",
432 reg = <0x9800 0x0 0x0 0x0 0x0>;
434 interrupt-parent = <&pic>;
436 #address-cells = <3>;
437 #size-cells = <2>;
439 #interrupt-cells = <1>;
440 interrupt-map-mask = <0 0 0 0>;
441 interrupt-map = <0 0 0 0 &pic 38 IRQ_TYPE_LEVEL_HIGH>;
445 pcie@14,0 {
446 compatible = "pci0014,7a19.1",
447 "pci0014,7a19",
451 reg = <0xa000 0x0 0x0 0x0 0x0>;
453 interrupt-parent = <&pic>;
455 #address-cells = <3>;
456 #size-cells = <2>;
458 #interrupt-cells = <1>;
459 interrupt-map-mask = <0 0 0 0>;
460 interrupt-map = <0 0 0 0 &pic 39 IRQ_TYPE_LEVEL_HIGH>;
467 #address-cells = <2>;
468 #size-cells = <1>;
469 ranges = <1 0 0 0x18000000 0x20000>;