Lines Matching +full:4 +full:d
29 * between mem locations with size of xfer spec'd in bytes
40 /* move d to return register as value of function */
43 addi r4, r0, 4 /* n = 4 */
48 andi r4, r5, 3 /* n = d & 3 */
51 /* n = 4 - n (yields 3, 2, 1 transfers for 1, 2, 3 addr offset) */
52 rsubi r4, r4, 4
59 sbi r11, r5, 0 /* *d = h */
61 addi r5, r5, 1 /* d++ */
81 lwi r10, r6, 4 /* t2 = *(s + 4) */
84 swi r9, r5, 0 /* *(d + 0) = t1 */
85 swi r10, r5, 4 /* *(d + 4) = t2 */
86 swi r11, r5, 8 /* *(d + 8) = t3 */
87 swi r12, r5, 12 /* *(d + 12) = t4 */
92 swi r9, r5, 16 /* *(d + 16) = t1 */
93 swi r10, r5, 20 /* *(d + 20) = t2 */
94 swi r11, r5, 24 /* *(d + 24) = t3 */
95 swi r12, r5, 28 /* *(d + 28) = t4 */
99 addi r5, r5, 32 /* d = d + 32 (IN DELAY SLOT) */
115 lwi r12, r8, 4 /* v = *(as + 4) */
118 swi r9, r5, 0 /* *(d + 0) = t1 */
123 swi r9, r5, 4 /* *(d + 4) = t1 */
128 swi r9, r5, 8 /* *(d + 8) = t1 */
133 swi r9, r5, 12 /* *(d + 12) = t1 */
138 swi r9, r5, 16 /* *(d + 16) = t1 */
143 swi r9, r5, 20 /* *(d + 20) = t1 */
148 swi r9, r5, 24 /* *(d + 24) = t1 */
153 swi r9, r5, 28 /* *(d + 28) = t1 */
158 addi r5, r5, 32 /* d = d + 32 (IN DELAY SLOT) */
164 lwi r12, r8, 4 /* v = *(as + 4) */
167 swi r9, r5, 0 /* *(d + 0) = t1 */
172 swi r9, r5, 4 /* *(d + 4) = t1 */
177 swi r9, r5, 8 /* *(d + 8) = t1 */
182 swi r9, r5, 12 /* *(d + 12) = t1 */
187 swi r9, r5, 16 /* *(d + 16) = t1 */
192 swi r9, r5, 20 /* *(d + 20) = t1 */
197 swi r9, r5, 24 /* *(d + 24) = t1 */
202 swi r9, r5, 28 /* *(d + 28) = t1 */
207 addi r5, r5, 32 /* d = d + 32 (IN DELAY SLOT) */
213 lwi r12, r8, 4 /* v = *(as + 4) */
216 swi r9, r5, 0 /* *(d + 0) = t1 */
221 swi r9, r5, 4 /* *(d + 4) = t1 */
226 swi r9, r5, 8 /* *(d + 8) = t1 */
231 swi r9, r5, 12 /* *(d + 12) = t1 */
236 swi r9, r5, 16 /* *(d + 16) = t1 */
241 swi r9, r5, 20 /* *(d + 20) = t1 */
246 swi r9, r5, 24 /* *(d + 24) = t1 */
251 swi r9, r5, 28 /* *(d + 28) = t1 */
256 addi r5, r5, 32 /* d = d + 32 (IN DELAY SLOT) */
259 addi r4, r0, 4 /* n = 4 */
273 sw r9, r5, r10 /* *(d+offset) = t1 */
274 addi r4, r4,-4 /* n-- */
276 addi r10, r10, 4 /* offset++ (IN DELAY SLOT) */
283 addi r8, r8, 4 /* as = as + 4 */
296 sw r9, r5, r10 /* *(d + offset) = t1 */
298 addi r4, r4,-4 /* n = n - 4 */
300 addi r10, r10, 4 /* offset = ofset + 4 (IN DELAY SLOT) */
310 sw r9, r5, r10 /* *(d + offset) = t1 */
312 addi r4, r4,-4 /* n = n - 4 */
314 addi r10, r10, 4 /* offset = ofset + 4 (IN DELAY SLOT) */
324 sw r9, r5, r10 /* *(d + offset) = t1 */
326 addi r4, r4,-4 /* n = n - 4 */
328 addi r10, r10, 4 /* offset = ofset + 4 (IN DELAY SLOT) */
331 add r5, r5, r10 /* d = d + offset */
340 sbi r9, r5, 0 /* *d = t1 */
343 addi r5, r5, 1 /* d++ (IN DELAY SLOT) */
357 cmpu r4, r5, r6 /* n = s - d */
361 /* move d to return register as value of function */
364 add r5, r5, r7 /* d = d + c */
367 addi r4, r0, 4 /* n = 4 */
372 andi r4, r5, 3 /* n = d & 3 */
381 addi r5, r5, -1 /* d-- */
383 sbi r11, r5, 0 /* *d = h */
403 addi r5, r5, -32 /* d = d - 32 */
408 swi r9, r5, 28 /* *(d + 28) = t1 */
409 swi r10, r5, 24 /* *(d + 24) = t2 */
410 swi r11, r5, 20 /* *(d + 20) = t3 */
411 swi r12, r5, 16 /* *(d + 16) = t4 */
414 lwi r11, r6, 4 /* t3 = *(s + 4) */
416 swi r9, r5, 12 /* *(d + 12) = t1 */
417 swi r10, r5, 8 /* *(d + 8) = t2 */
418 swi r11, r5, 4 /* *(d + 4) = t3 */
421 swi r12, r5, 0 /* *(d + 0) = t4 (IN DELAY SLOT) */
438 addi r5, r5, -32 /* d = d - 32 */
442 swi r9, r5, 28 /* *(d + 28) = t1 */
447 swi r9, r5, 24 /* *(d + 24) = t1 */
452 swi r9, r5, 20 /* *(d + 20) = t1 */
457 swi r9, r5, 16 /* *(d + 16) = t1 */
462 swi r9, r5, 12 /* *(d + 112) = t1 */
467 swi r9, r5, 8 /* *(d + 8) = t1 */
469 lwi r12, r8, 4 /* v = *(as + 4) */
472 swi r9, r5, 4 /* *(d + 4) = t1 */
477 swi r9, r5, 0 /* *(d + 0) = t1 */
487 addi r5, r5, -32 /* d = d - 32 */
491 swi r9, r5, 28 /* *(d + 28) = t1 */
496 swi r9, r5, 24 /* *(d + 24) = t1 */
501 swi r9, r5, 20 /* *(d + 20) = t1 */
506 swi r9, r5, 16 /* *(d + 16) = t1 */
511 swi r9, r5, 12 /* *(d + 112) = t1 */
516 swi r9, r5, 8 /* *(d + 8) = t1 */
518 lwi r12, r8, 4 /* v = *(as + 4) */
521 swi r9, r5, 4 /* *(d + 4) = t1 */
526 swi r9, r5, 0 /* *(d + 0) = t1 */
536 addi r5, r5, -32 /* d = d - 32 */
540 swi r9, r5, 28 /* *(d + 28) = t1 */
545 swi r9, r5, 24 /* *(d + 24) = t1 */
550 swi r9, r5, 20 /* *(d + 20) = t1 */
555 swi r9, r5, 16 /* *(d + 16) = t1 */
560 swi r9, r5, 12 /* *(d + 112) = t1 */
565 swi r9, r5, 8 /* *(d + 8) = t1 */
567 lwi r12, r8, 4 /* v = *(as + 4) */
570 swi r9, r5, 4 /* *(d + 4) = t1 */
575 swi r9, r5, 0 /* *(d + 0) = t1 */
581 addi r4, r0, 4 /* n = 4 */
587 rsub r5, r4, r5 /* d = d - n */
596 addi r4, r4,-4 /* n-- */
599 sw r9, r5, r4 /* *(d+n) = t1 (IN DELAY SLOT) */
615 addi r4, r4,-4 /* n = n - 4 */
619 sw r9, r5, r4 /* *(d + n) = t1 */
628 addi r4, r4,-4 /* n = n - 4 */
632 sw r9, r5, r4 /* *(d + n) = t1 */
641 addi r4, r4,-4 /* n = n - 4 */
645 sw r9, r5, r4 /* *(d + n) = t1 */
656 addi r5, r5, -1 /* d-- */
657 sbi r9, r5, 0 /* *d = t1 */