Lines Matching full:exception

3  * Exception handling for Microblaze
18  *		Low-level exception handers, MMU support, and rewrite.
45  * Microblaze HW Exception Handler
46  * - Non self-modifying exception handler for the following exception conditions
53  *   - Privileged instruction exception (MMU)
54  *   - Data storage exception (MMU)
55  *   - Instruction storage exception (MMU)
56  *   - Data TLB miss exception (MMU)
57  *   - Instruction TLB miss exception (MMU)
59  * Note we disable interrupts during exception handling, otherwise we will
190 .extern other_exception_handler /* Defined in exception.c */
195  * Exception handler notes:
232  * MMU exception handler has different handling compare to no MMU kernel.
233  * Exception handler use jump table for directing of what happen. For MMU kernel
234  * is this approach better because MMU relate exception are handled by asm code
235  * in this file. In compare to with MMU expect of unaligned exception
242  * return from exception
252 /* Create space for exception counting. */
257 	/* Look at exception vector table. There is 32 exceptions * word size */
266 /*  1 - Unaligned data access exception */
268 /*  2 - Illegal op-code exception */
270 /*  3 - Instruction bus error exception */
272 /*  4 - Data bus error exception */
274 /*  5 - Divide by zero exception */
276 /*  6 - Floating point unit exception */
278 /*  7 - Privileged instruction exception */
289 /* 16 - Data storage exception */
291 /* 17 - Instruction storage exception */
293 /* 18 - Data TLB miss exception */
295 /* 19 - Instruction TLB miss exception */
339 	/* Calculate exception vector offset = r5 << 2 */
344 /* counting which exception happen */
353 	/* Load the HW Exception vector */
361 /* 0x01 - Unaligned data access exception
396 	lbui	r5, r3, 0; /* Exception address in r3 */
410 	lbui	r5, r3, 0; /* Exception address in r3 */
428 ex_lw_end: /* Exception handling of load word, ends */
464 ex_sw_end: /* Exception handling of store word, ends. */
471 	/* Exception vector entry code. This code runs with address translation
474 	/* Exception vectors. */
476 	/* 0x10 - Data Storage Exception
572 		/* The bailout. Restore registers to pre-exception conditions
581 	/* 0x11 - Instruction Storage Exception
591 	/* 0x12 - Data TLB Miss Exception
653 		/* The bailout. Restore registers to pre-exception conditions
662 	/* 0x13 - Instruction TLB Miss Exception
724 		/* The bailout. Restore registers to pre-exception conditions
816 /* Unaligned data access exception last on a 4k page for MMU.
836 load1:	lbui	r5, r4, 0;	/* Exception address in r4 - delay slot */
861 ex_lw_end_vm:			/* Exception handling of load word, ends */
897 ex_sw_end_vm:			/* Exception handling of store word, ends. */
910 	 * in PT_PC which is used as return address from exception */
933 /* FIXME add handle function for unhandled exception - dump register */
938  * - Contains code snippets for each register that caused the unalign exception
939  * - Hence exception handler is NOT self-modifying