2  * I/O Processor (IOP) management
16  * The IOP chips are used in the IIfx and some Quadras (900, 950) to manage
19  * 990429 (jmt) - Initial implementation, just enough to knock the SCC IOP
22  * 990603 (jmt) - Added code to grab the correct ISM IOP interrupt for OSS
26  * 990605 (jmt) - Rearranged things a bit wrt IOP detection; iop_present is
27  *		  gone, IOP base addresses are now in an array and the
28  *		  globally-visible functions take an IOP number instead of
33  *		  IOP. The trick now is figuring out the message formats.
41  *		  unsolicited messages from the IOP (and our replies to them
45  * 990729 (jmt) - Added passing of pt_regs structure to IOP handlers. This is
50  * o The SCC IOP has to be placed in bypass mode before the serial console
55  *   IOP hasn't died.
56  * o Some of the IOP manager routines need better error checking and
62  * IOP Message Passing 101
66  * a shared memory area in the IOP RAM. Each IOP has seven "channels"; each
67  * channel is connected to a specific software driver on the IOP. For example
68  * on the SCC IOP there is one channel for each serial port. Each channel has
73  * buffer, set the state to MSG_NEW and signal the IOP by setting the IRQ flag
74  * in the IOP control to 1. The IOP will move the state to MSG_RCVD when it
80  * To receive message from the IOP the same procedure is used except the roles
81  * are reversed. That is, the IOP puts message in the channel with a state of
84  * has been placed back in the receive channel. The IOP will then reset the
88  * interrupt level; they are distinguished by a pair of bits in the IOP status
89  * register. The IOP will raise INT0 when one or more messages in the send
100  * a message is received on that IOP/channel combination. The handlers are
102  * from the IOP. The message state will be in MSG_RCVD while the handler runs;
105  * the IOP. This two-step process is provided to allow the handler to defer
148  * IOP structures for the two IOPs
150  * The SCC IOP controls both serial ports (A and B) as its two functions.
151  * The ISM IOP controls the SWIM (floppy drive) and ADB.
157  * IOP message queues
170 static __inline__ void iop_loadaddr(volatile struct mac_iop *iop, __u16 addr)  in iop_loadaddr()  argument
172 	iop->ram_addr_lo = addr;  in iop_loadaddr()
173 	iop->ram_addr_hi = addr >> 8;  in iop_loadaddr()
176 static __inline__ __u8 iop_readb(volatile struct mac_iop *iop, __u16 addr)  in iop_readb()  argument
178 	iop->ram_addr_lo = addr;  in iop_readb()
179 	iop->ram_addr_hi = addr >> 8;  in iop_readb()
180 	return iop->ram_data;  in iop_readb()
183 static __inline__ void iop_writeb(volatile struct mac_iop *iop, __u16 addr, __u8 data)  in iop_writeb()  argument
185 	iop->ram_addr_lo = addr;  in iop_writeb()
186 	iop->ram_addr_hi = addr >> 8;  in iop_writeb()
187 	iop->ram_data = data;  in iop_writeb()
190 static __inline__ void iop_stop(volatile struct mac_iop *iop)  in iop_stop()  argument
192 	iop->status_ctrl = IOP_AUTOINC;  in iop_stop()
195 static __inline__ void iop_start(volatile struct mac_iop *iop)  in iop_start()  argument
197 	iop->status_ctrl = IOP_RUN | IOP_AUTOINC;  in iop_start()
200 static __inline__ void iop_interrupt(volatile struct mac_iop *iop)  in iop_interrupt()  argument
202 	iop->status_ctrl = IOP_IRQ | IOP_RUN | IOP_AUTOINC;  in iop_interrupt()
205 static int iop_alive(volatile struct mac_iop *iop)  in iop_alive()  argument
209 	retval = (iop_readb(iop, IOP_ADDR_ALIVE) == 0xFF);  in iop_alive()
210 	iop_writeb(iop, IOP_ADDR_ALIVE, 0);  in iop_alive()
247 		pr_debug("SCC IOP detected at %p\n", iop_base[IOP_NUM_SCC]);  in iop_init()
255 		pr_debug("ISM IOP detected at %p\n", iop_base[IOP_NUM_ISM]);  in iop_init()
287 					"ISM IOP", (void *)IOP_NUM_ISM))  in iop_register_interrupts()
288 				pr_err("Couldn't register ISM IOP interrupt\n");  in iop_register_interrupts()
290 			if (request_irq(IRQ_VIA2_0, iop_ism_irq, 0, "ISM IOP",  in iop_register_interrupts()
292 				pr_err("Couldn't register ISM IOP interrupt\n");  in iop_register_interrupts()
295 			pr_warn("IOP: oh my god, they killed the ISM IOP!\n");  in iop_register_interrupts()
297 			pr_warn("IOP: the ISM IOP seems to be alive.\n");  in iop_register_interrupts()
303  * Register or unregister a listener for a specific IOP and channel
325  * notifying the IOP.
356 	volatile struct mac_iop *iop = iop_base[msg->iop_num];  in iop_do_send()  local
365 		iop_writeb(iop, offset, msg->message[i]);  in iop_do_send()
368 	iop_writeb(iop, IOP_ADDR_SEND_STATE + msg->channel, IOP_MSG_NEW);  in iop_do_send()
370 	iop_interrupt(iop);  in iop_do_send()
380 	volatile struct mac_iop *iop = iop_base[iop_num];  in iop_handle_send()  local
384 	iop_writeb(iop, IOP_ADDR_SEND_STATE + chan, IOP_MSG_IDLE);  in iop_handle_send()
391 		msg->reply[i] = iop_readb(iop, offset);  in iop_handle_send()
400 	if (msg && iop_readb(iop, IOP_ADDR_SEND_STATE + chan) == IOP_MSG_IDLE)  in iop_handle_send()
411 	volatile struct mac_iop *iop = iop_base[iop_num];  in iop_handle_recv()  local
424 		msg->message[i] = iop_readb(iop, offset);  in iop_handle_recv()
429 	iop_writeb(iop, IOP_ADDR_RECV_STATE + chan, IOP_MSG_RCVD);  in iop_handle_recv()
483  * Upload code to the shared RAM of an IOP.
499  * Download code from the shared RAM of an IOP.
515  * Compare the code in the shared RAM of an IOP with a copy in system memory
537  * Handle an ISM IOP interrupt
543 	volatile struct mac_iop *iop = iop_base[iop_num];  in iop_ism_irq()  local
545 	u8 events = iop->status_ctrl & (IOP_INT0 | IOP_INT1);  in iop_ism_irq()
549 			     iop->status_ctrl);  in iop_ism_irq()
553 			iop->status_ctrl = IOP_INT0 | IOP_RUN | IOP_AUTOINC;  in iop_ism_irq()
555 				state = iop_readb(iop, IOP_ADDR_SEND_STATE + i);  in iop_ism_irq()
566 			iop->status_ctrl = IOP_INT1 | IOP_RUN | IOP_AUTOINC;  in iop_ism_irq()
568 				state = iop_readb(iop, IOP_ADDR_RECV_STATE + i);  in iop_ism_irq()
577 		events = iop->status_ctrl & (IOP_INT0 | IOP_INT1);  in iop_ism_irq()