Lines Matching +full:1 +full:- +full:bit +full:- +full:only
1 /* SPDX-License-Identifier: GPL-2.0 */
6 * via them as are assorted bits and bobs - eg rtc, adb. The picture
7 * is a bit incomplete as the Mac documentation doesn't cover this well
51 * is the bit to flip screen buffers.
52 * 0=alternate, 1=main.
53 * on II,IIx,IIcx,IIci,IIfx this is a bit
54 * for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
59 * state-control line SEL" on all but IIfx
62 * this bit enables the "Overlay" address
65 * vector. 1=use overlay map.
66 * On the IIci,IIfx it is another bit of the
67 * CPU ID: 0=normal IIci, 1=IIci with parity
76 * 1: select the external serial clock to
83 /* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
85 * On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
86 * bit 2: 1=IIci, 0=IIfx
87 * bit 1: 1 on both IIci and IIfx.
88 * MkLinux sez bit 0 is 'burnin flag' in this case.
89 * CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
93 #define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
94 #define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
95 #define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
96 #define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
103 * 0=error, 1=OK. */
104 #define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
108 #define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
109 #define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
112 #define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
113 #define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
117 * correspond to a VIA work-alike named 'EVR'. */
132 * defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
136 #define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
137 #define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
148 * 0 1 1 Mbit
149 * 1 0 4 Mbit
150 * 1 1 16 Mbit
160 * [MkLinux] RBV_PARODD: 1=odd,0=even. */
163 #define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
164 #define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
165 #define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
167 * if AMU, 0=24bit to 32bit translation
168 * if PMMU, 1=PMMU is accessing page table.
177 #define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
183 * of the alternate video page for page-flipping animation. Since there
185 * right bit in the VIA chip (6522 Versatile Interface Adapter).
190 * 6522 registers - see databook.
198 #define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
199 #define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
200 #define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
201 #define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
202 #define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
203 #define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
204 #define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
205 #define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
206 #define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
207 #define vSR 0x1400 /* [VIA only] Shift register. */
208 #define vACR 0x1600 /* [VIA only] Auxiliary control register. */
209 #define vPCR 0x1800 /* [VIA only] Peripheral control register. */
217 /* The RBV only decodes the bottom eight address lines; the VIA doesn't
218 * decode the bottom eight -- so vBufB | rBufB will always get you BufB */
219 /* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
223 * Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
227 #define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
228 #define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
230 #define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
231 #define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
232 #define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
239 #define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
241 #define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
243 #define MON_15BW (1<<3) /* 15" BW portrait. */
250 #define IER_SET_BIT(b) (0x80 | (1<<(b)) )
251 #define IER_CLR_BIT(b) (0x7F & (1<<(b)) )