Lines Matching +full:can +full:- +full:clock +full:- +full:select
1 # SPDX-License-Identifier: GPL-2.0
13 applications, and are all System-On-Chip (SOC) devices, as opposed
17 MC68xxx processor, select M68KCLASSIC.
19 processor, select COLDFIRE.
23 select HAVE_ARCH_PFN_VALID
24 select M68020 if MMU && !(M68030 || M68040 || M68060)
28 select CPU_HAS_NO_BITFIELDS
29 select CPU_HAS_NO_CAS
30 select CPU_HAS_NO_MULDIV64
31 select GENERIC_CSUM
32 select GPIOLIB
33 select HAVE_LEGACY_CLK
34 select HAVE_PAGE_SIZE_8KB if !MMU
39 select HAVE_ARCH_PFN_VALID
40 select LEGACY_TIMER_TICK
41 select NO_DMA
42 select M68020
53 select CPU_HAS_NO_BITFIELDS
54 select CPU_HAS_NO_CAS
55 select CPU_HAS_NO_MULDIV64
56 select CPU_HAS_NO_UNALIGNED
57 select GENERIC_CSUM
58 select CPU_NO_EFFICIENT_FFS
59 select HAVE_ARCH_HASH
60 select HAVE_PAGE_SIZE_4KB
61 select LEGACY_TIMER_TICK
66 System-On-Chip devices (eg 68328, 68302, etc). It does not contain
72 select FPU
73 select CPU_HAS_ADDRESS_SPACES
84 select FPU
85 select CPU_HAS_ADDRESS_SPACES
93 select FPU
94 select CPU_HAS_ADDRESS_SPACES
103 select FPU
104 select CPU_HAS_ADDRESS_SPACES
114 select M68000
121 select M68000
128 select M68000
138 Select the type of ColdFire System-on-Chip (SoC) that you want
144 select COLDFIRE_SW_A7
145 select COLDFIRE_TIMERS
146 select HAVE_MBAR
147 select CPU_NO_EFFICIENT_FFS
154 select COLDFIRE_SW_A7
155 select COLDFIRE_TIMERS
156 select HAVE_MBAR
157 select CPU_NO_EFFICIENT_FFS
164 select COLDFIRE_PIT_TIMER
165 select HAVE_CACHE_SPLIT
172 select COLDFIRE_PIT_TIMER
173 select HAVE_CACHE_SPLIT
174 select HAVE_IPSBAR
181 select COLDFIRE_SW_A7
182 select COLDFIRE_TIMERS
183 select HAVE_MBAR
184 select CPU_NO_EFFICIENT_FFS
191 select COLDFIRE_SW_A7
192 select COLDFIRE_TIMERS
193 select HAVE_MBAR
194 select CPU_NO_EFFICIENT_FFS
201 select COLDFIRE_PIT_TIMER
202 select M527x
203 select HAVE_CACHE_SPLIT
204 select HAVE_IPSBAR
211 select COLDFIRE_SW_A7
212 select COLDFIRE_TIMERS
213 select HAVE_MBAR
214 select CPU_NO_EFFICIENT_FFS
221 select COLDFIRE_PIT_TIMER
222 select M527x
223 select HAVE_CACHE_SPLIT
224 select HAVE_IPSBAR
231 select COLDFIRE_PIT_TIMER
232 select HAVE_CACHE_SPLIT
233 select HAVE_IPSBAR
240 select COLDFIRE_TIMERS
241 select COLDFIRE_SW_A7
242 select HAVE_CACHE_CB
243 select HAVE_MBAR
244 select CPU_NO_EFFICIENT_FFS
251 select COLDFIRE_TIMERS
252 select M53xx
253 select HAVE_CACHE_CB
260 select COLDFIRE_TIMERS
261 select M53xx
262 select HAVE_CACHE_CB
269 select COLDFIRE_SW_A7
270 select COLDFIRE_TIMERS
271 select HAVE_CACHE_CB
272 select HAVE_MBAR
273 select CPU_NO_EFFICIENT_FFS
279 select M54xx
280 select COLDFIRE_SLTIMERS
281 select MMU_COLDFIRE if MMU
282 select FPU if MMU
283 select HAVE_CACHE_CB
284 select HAVE_MBAR
285 select CPU_NO_EFFICIENT_FFS
291 select COLDFIRE_SLTIMERS
292 select MMU_COLDFIRE if MMU
293 select FPU if MMU
294 select M54xx
295 select HAVE_CACHE_CB
296 select HAVE_MBAR
297 select CPU_NO_EFFICIENT_FFS
303 select COLDFIRE_PIT_TIMER
304 select MMU_COLDFIRE if MMU
305 select HAVE_CACHE_CB
318 select HAVE_PCI
326 select LEGACY_TIMER_TICK
330 select LEGACY_TIMER_TICK
340 At some point in the future, this will cause floating-point math
342 floating-point math coprocessor. Thrill-seekers and chronically
343 sleep-deprived psychotic hacker types can say Y now, everyone else
351 correct rounding, the emulator can (often) do the same but this
352 extra calculation can cost quite some time, so you can disable
361 This option prevents any floating-point instructions from being
364 kernel will only be usable on machines without a floating-point
366 needs to be executed whether a floating-point instruction in the
385 bool "Use read-modify-write instructions"
389 read-modify-write bus cycles. While this is faster than the
390 workaround of disabling interrupts, it can conflict with DMA
394 configuration where it should work are 68030-based Ataris, where it
418 defines the maximal power of two of number of pages that can be
430 bool "Use write-through caching for 68060 supervisor accesses"
434 Copyback caching means that memory writes will be held in an on-chip
463 select ALTERNATE_USER_ADDRESS_SPACE
484 int "Set the core clock frequency"
496 Define the CPU clock frequency in use. This is the core clock
497 frequency, it may or may not be the same as the external clock
499 PLL and can have their frequency programmed at run time, others
540 bool "Write-through"
542 The ColdFire CPU cache is set into Write-through mode.
545 bool "Copy-back"
547 The ColdFire CPU cache is set into Copy-back mode.
551 # Coldfire cores that do not have a data cache configured can do coherent DMA.