Lines Matching +full:0 +full:x3e0
11 #define PCH_PIC_SIZE 0x3e8
13 #define PCH_PIC_INT_ID_START 0x0
14 #define PCH_PIC_INT_ID_END 0x7
15 #define PCH_PIC_MASK_START 0x20
16 #define PCH_PIC_MASK_END 0x27
17 #define PCH_PIC_HTMSI_EN_START 0x40
18 #define PCH_PIC_HTMSI_EN_END 0x47
19 #define PCH_PIC_EDGE_START 0x60
20 #define PCH_PIC_EDGE_END 0x67
21 #define PCH_PIC_CLEAR_START 0x80
22 #define PCH_PIC_CLEAR_END 0x87
23 #define PCH_PIC_AUTO_CTRL0_START 0xc0
24 #define PCH_PIC_AUTO_CTRL0_END 0xc7
25 #define PCH_PIC_AUTO_CTRL1_START 0xe0
26 #define PCH_PIC_AUTO_CTRL1_END 0xe7
27 #define PCH_PIC_ROUTE_ENTRY_START 0x100
28 #define PCH_PIC_ROUTE_ENTRY_END 0x13f
29 #define PCH_PIC_HTMSI_VEC_START 0x200
30 #define PCH_PIC_HTMSI_VEC_END 0x23f
31 #define PCH_PIC_INT_IRR_START 0x380
32 #define PCH_PIC_INT_IRR_END 0x38f
33 #define PCH_PIC_INT_ISR_START 0x3a0
34 #define PCH_PIC_INT_ISR_END 0x3af
35 #define PCH_PIC_POLARITY_START 0x3e0
36 #define PCH_PIC_POLARITY_END 0x3e7
37 #define PCH_PIC_INT_ID_VAL 0x7000000UL
38 #define PCH_PIC_INT_ID_VER 0x1UL
44 uint64_t mask; /* 1:disable irq, 0:enable irq */
46 uint64_t edge; /* 1:edge triggered, 0:level triggered */
52 uint64_t polarity; /* 0: high level trigger, 1: low level trigger */
53 uint8_t route_entry[64]; /* default value 0, route to int0: eiointc */