1 /* SPDX-License-Identifier: GPL-2.0 */
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
37 enum reg0i15_op {
41 enum reg0i26_op {
46 enum reg1i20_op {
55 enum reg1i21_op {
62 enum reg2_op {
82 enum reg2i5_op {
88 enum reg2i6_op {
94 enum reg2i12_op {
118 enum reg2i14_op {
129 enum reg2i16_op {
139 enum reg2bstrd_op {
144 enum reg3_op {
254 enum reg3sa2_op {
375 enum loongarch_gpr {
414 	return val & (1UL << (bit - 1));  in is_imm_negative()
419 	return ip->reg0i15_format.opcode == break_op;  in is_break_ins()
424 	return ip->reg1i20_format.opcode >= pcaddi_op &&  in is_pc_ins()
425 			ip->reg1i20_format.opcode <= pcaddu18i_op;  in is_pc_ins()
430 	return ip->reg1i21_format.opcode >= beqz_op &&  in is_branch_ins()
431 		ip->reg1i21_format.opcode <= bgeu_op;  in is_branch_ins()
437 	return ip->reg2i12_format.opcode == std_op &&  in is_ra_save_ins()
438 		ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&  in is_ra_save_ins()
439 		ip->reg2i12_format.rd == LOONGARCH_GPR_RA &&  in is_ra_save_ins()
440 		!is_imm12_negative(ip->reg2i12_format.immediate);  in is_ra_save_ins()
445 	/* addi.d $sp, $sp, -imm */  in is_stack_alloc_ins()
446 	return ip->reg2i12_format.opcode == addid_op &&  in is_stack_alloc_ins()
447 		ip->reg2i12_format.rj == LOONGARCH_GPR_SP &&  in is_stack_alloc_ins()
448 		ip->reg2i12_format.rd == LOONGARCH_GPR_SP &&  in is_stack_alloc_ins()
449 		is_imm12_negative(ip->reg2i12_format.immediate);  in is_stack_alloc_ins()
454 	switch (ip->reg0i26_format.opcode) {  in is_self_loop_ins()
457 		if (ip->reg0i26_format.immediate_l == 0  in is_self_loop_ins()
458 		    && ip->reg0i26_format.immediate_h == 0)  in is_self_loop_ins()
462 	switch (ip->reg1i21_format.opcode) {  in is_self_loop_ins()
466 		if (ip->reg1i21_format.immediate_l == 0  in is_self_loop_ins()
467 		    && ip->reg1i21_format.immediate_h == 0)  in is_self_loop_ins()
471 	switch (ip->reg2i16_format.opcode) {  in is_self_loop_ins()
478 		if (ip->reg2i16_format.immediate == 0)  in is_self_loop_ins()
482 		if (regs->regs[ip->reg2i16_format.rj] +  in is_self_loop_ins()
483 		    ((unsigned long)ip->reg2i16_format.immediate << 2) == (unsigned long)ip)  in is_self_loop_ins()
507 u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);
508 u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
510 u32 larch_insn_gen_lu12iw(enum loongarch_gpr rd, int imm);
511 u32 larch_insn_gen_lu32id(enum loongarch_gpr rd, int imm);
512 u32 larch_insn_gen_lu52id(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
513 u32 larch_insn_gen_jirl(enum loongarch_gpr rd, enum loongarch_gpr rj, int imm);
517 	return -(1L << (bit - 1)) <= val && val < (1L << (bit - 1));  in signed_imm_check()
525 #define DEF_EMIT_REG0I15_FORMAT(NAME, OP)				\  argument
526 static inline void emit_##NAME(union loongarch_instruction *insn,	\
529 	insn->reg0i15_format.opcode = OP;				\
530 	insn->reg0i15_format.immediate = imm;				\
538 #define DEF_EMIT_REG0I26_FORMAT(NAME, OP)				\  in DEF_EMIT_REG0I15_FORMAT()  argument
539 static inline void emit_##NAME(union loongarch_instruction *insn,	\  in DEF_EMIT_REG0I15_FORMAT()
548 	insn->reg0i26_format.opcode = OP;				\  in DEF_EMIT_REG0I15_FORMAT()
549 	insn->reg0i26_format.immediate_l = immediate_l;			\  in DEF_EMIT_REG0I15_FORMAT()
550 	insn->reg0i26_format.immediate_h = immediate_h;			\  in DEF_EMIT_REG0I15_FORMAT()
556 #define DEF_EMIT_REG1I20_FORMAT(NAME, OP)				\  argument
557 static inline void emit_##NAME(union loongarch_instruction *insn,	\
558 			       enum loongarch_gpr rd, int imm)		\
560 	insn->reg1i20_format.opcode = OP;				\
561 	insn->reg1i20_format.immediate = imm;				\
562 	insn->reg1i20_format.rd = rd;					\
569 #define DEF_EMIT_REG2_FORMAT(NAME, OP)					\  argument
570 static inline void emit_##NAME(union loongarch_instruction *insn,	\
571 			       enum loongarch_gpr rd,			\
572 			       enum loongarch_gpr rj)			\
574 	insn->reg2_format.opcode = OP;					\
575 	insn->reg2_format.rd = rd;					\
576 	insn->reg2_format.rj = rj;					\
585 #define DEF_EMIT_REG2I5_FORMAT(NAME, OP)				\  argument
586 static inline void emit_##NAME(union loongarch_instruction *insn,	\
587 			       enum loongarch_gpr rd,			\
588 			       enum loongarch_gpr rj,			\
591 	insn->reg2i5_format.opcode = OP;				\
592 	insn->reg2i5_format.immediate = imm;				\
593 	insn->reg2i5_format.rd = rd;					\
594 	insn->reg2i5_format.rj = rj;					\
601 #define DEF_EMIT_REG2I6_FORMAT(NAME, OP)				\  argument
602 static inline void emit_##NAME(union loongarch_instruction *insn,	\
603 			       enum loongarch_gpr rd,			\
604 			       enum loongarch_gpr rj,			\
607 	insn->reg2i6_format.opcode = OP;				\
608 	insn->reg2i6_format.immediate = imm;				\
609 	insn->reg2i6_format.rd = rd;					\
610 	insn->reg2i6_format.rj = rj;					\
617 #define DEF_EMIT_REG2I12_FORMAT(NAME, OP)				\  argument
618 static inline void emit_##NAME(union loongarch_instruction *insn,	\
619 			       enum loongarch_gpr rd,			\
620 			       enum loongarch_gpr rj,			\
623 	insn->reg2i12_format.opcode = OP;				\
624 	insn->reg2i12_format.immediate = imm;				\
625 	insn->reg2i12_format.rd = rd;					\
626 	insn->reg2i12_format.rj = rj;					\
647 #define DEF_EMIT_REG2I14_FORMAT(NAME, OP)				\  argument
648 static inline void emit_##NAME(union loongarch_instruction *insn,	\
649 			       enum loongarch_gpr rd,			\
650 			       enum loongarch_gpr rj,			\
653 	insn->reg2i14_format.opcode = OP;				\
654 	insn->reg2i14_format.immediate = imm;				\
655 	insn->reg2i14_format.rd = rd;					\
656 	insn->reg2i14_format.rj = rj;					\
668 #define DEF_EMIT_REG2I16_FORMAT(NAME, OP)				\  argument
669 static inline void emit_##NAME(union loongarch_instruction *insn,	\
670 			       enum loongarch_gpr rj,			\
671 			       enum loongarch_gpr rd,			\
674 	insn->reg2i16_format.opcode = OP;				\
675 	insn->reg2i16_format.immediate = offset;			\
676 	insn->reg2i16_format.rj = rj;					\
677 	insn->reg2i16_format.rd = rd;					\
688 			     enum loongarch_gpr rd,
689 			     enum loongarch_gpr rj,
692 	insn->reg2i16_format.opcode = jirl_op;
693 	insn->reg2i16_format.immediate = offset;
694 	insn->reg2i16_format.rd = rd;
695 	insn->reg2i16_format.rj = rj;
698 #define DEF_EMIT_REG2BSTRD_FORMAT(NAME, OP)				\  argument
699 static inline void emit_##NAME(union loongarch_instruction *insn,	\
700 			       enum loongarch_gpr rd,			\
701 			       enum loongarch_gpr rj,			\
705 	insn->reg2bstrd_format.opcode = OP;				\
706 	insn->reg2bstrd_format.msbd = msbd;				\
707 	insn->reg2bstrd_format.lsbd = lsbd;				\
708 	insn->reg2bstrd_format.rj = rj;					\
709 	insn->reg2bstrd_format.rd = rd;					\
714 #define DEF_EMIT_REG3_FORMAT(NAME, OP)					\  argument
715 static inline void emit_##NAME(union loongarch_instruction *insn,	\
716 			       enum loongarch_gpr rd,			\
717 			       enum loongarch_gpr rj,			\
718 			       enum loongarch_gpr rk)			\
720 	insn->reg3_format.opcode = OP;					\
721 	insn->reg3_format.rd = rd;					\
722 	insn->reg3_format.rj = rj;					\
723 	insn->reg3_format.rk = rk;					\
765 #define DEF_EMIT_REG3SA2_FORMAT(NAME, OP)				\  argument
766 static inline void emit_##NAME(union loongarch_instruction *insn,	\
767 			       enum loongarch_gpr rd,			\
768 			       enum loongarch_gpr rj,			\
769 			       enum loongarch_gpr rk,			\
772 	insn->reg3sa2_format.opcode = OP;				\
773 	insn->reg3sa2_format.immediate = imm;				\
774 	insn->reg3sa2_format.rd = rd;					\
775 	insn->reg3sa2_format.rj = rj;					\
776 	insn->reg3sa2_format.rk = rk;					\