Lines Matching full:res0
121 res0 = "UL(0)"
134 define(reg "_RES0", "(" res0 ")")
140 res0 = null
160 res0 = "UL(0)"
184 if (res0 != null)
185 define(reg "_RES0", "(" res0 ")")
190 if (res0 != null || res1 != null || unkn != null)
199 res0 = null
219 res0 = null
227 /^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
229 parse_bitdef(reg, "RES0", $2)
232 res0 = res0 " | GENMASK_ULL(" msb ", " lsb ")"