23 #define A64_COMP_BRANCH(sf, Rt, offset, type) \  argument
24 	aarch64_insn_gen_comp_branch_imm(0, offset, Rt, A64_VARIANT(sf), \
26 #define A64_CBZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, ZERO)  argument
27 #define A64_CBNZ(sf, Rt, imm19) A64_COMP_BRANCH(sf, Rt, (imm19) << 2, NONZERO)  argument
56 #define A64_LS_REG(Rt, Rn, Rm, size, type) \  argument
57 	aarch64_insn_gen_load_store_reg(Rt, Rn, Rm, \
73 #define A64_LS_IMM(Rt, Rn, imm, size, type) \  argument
74 	aarch64_insn_gen_load_store_imm(Rt, Rn, imm, \
96 #define A64_LS_PAIR(Rt, Rt2, Rn, offset, ls, type) \  argument
97 	aarch64_insn_gen_load_store_pair(Rt, Rt2, Rn, offset, \
100 /* Rn -= 16; Rn[0] = Rt; Rn[8] = Rt2; */
101 #define A64_PUSH(Rt, Rt2, Rn) A64_LS_PAIR(Rt, Rt2, Rn, -16, STORE, PRE_INDEX)  argument
102 /* Rt = Rn[0]; Rt2 = Rn[8]; Rn += 16; */
103 #define A64_POP(Rt, Rt2, Rn)  A64_LS_PAIR(Rt, Rt2, Rn, 16, LOAD, POST_INDEX)  argument
108 #define A64_LSX(sf, Rt, Rn, Rs, type) \  argument
109 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
111 /* Rt = [Rn]; (atomic) */
112 #define A64_LDXR(sf, Rt, Rn) \  argument
113 	A64_LSX(sf, Rt, Rn, A64_ZR, LOAD_EX)
114 /* [Rn] = Rt; (atomic) Rs = [state] */
115 #define A64_STXR(sf, Rt, Rn, Rs) \  argument
116 	A64_LSX(sf, Rt, Rn, Rs, STORE_EX)
117 /* [Rn] = Rt (store release); (atomic) Rs = [state] */
118 #define A64_STLXR(sf, Rt, Rn, Rs) \  argument
119 	aarch64_insn_gen_load_store_ex(Rt, Rn, Rs, A64_SIZE(sf), \
138 #define A64_LD_OP_AL(sf, Rt, Rn, Rs, op) \  argument
139 	aarch64_insn_gen_atomic_ld_op(Rt, Rn, Rs, \
142 /* Rt = [Rn] (load acquire); [Rn] <op>= Rs (store release) */
143 #define A64_LDADDAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, ADD)  argument
144 #define A64_LDCLRAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, CLR)  argument
145 #define A64_LDEORAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, EOR)  argument
146 #define A64_LDSETAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SET)  argument
147 /* Rt = [Rn] (load acquire); [Rn] = Rs (store release) */
148 #define A64_SWPAL(sf, Rt, Rn, Rs) A64_LD_OP_AL(sf, Rt, Rn, Rs, SWP)  argument
149 /* Rs = CAS(Rn, Rs, Rt) (load acquire & store release) */
150 #define A64_CASAL(sf, Rt, Rn, Rs) \  argument
151 	aarch64_insn_gen_cas(Rt, Rn, Rs, A64_SIZE(sf), \
301 #define A64_MRS_TPIDR_EL1(Rt) \  argument
302 	aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL1)
303 #define A64_MRS_TPIDR_EL2(Rt) \  argument
304 	aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_TPIDR_EL2)
305 #define A64_MRS_SP_EL0(Rt) \  argument
306 	aarch64_insn_gen_mrs(Rt, AARCH64_INSN_SYSREG_SP_EL0)