Lines Matching +full:fiq +full:- +full:index
1 // SPDX-License-Identifier: GPL-2.0-only
3 #include <linux/irqchip/arm-gic-v3.h>
25 struct vgic_v3_cpu_if *cpuif = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_underflow()
27 cpuif->vgic_hcr |= ICH_HCR_UIE; in vgic_v3_set_underflow()
38 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_fold_lr_state()
39 struct vgic_v3_cpu_if *cpuif = &vgic_cpu->vgic_v3; in vgic_v3_fold_lr_state()
40 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_fold_lr_state()
45 cpuif->vgic_hcr &= ~ICH_HCR_UIE; in vgic_v3_fold_lr_state()
47 for (lr = 0; lr < cpuif->used_lrs; lr++) { in vgic_v3_fold_lr_state()
48 u64 val = cpuif->vgic_lr[lr]; in vgic_v3_fold_lr_state()
64 /* Notify fds when the guest EOI'ed a level-triggered IRQ */ in vgic_v3_fold_lr_state()
65 if (lr_signals_eoi_mi(val) && vgic_valid_spi(vcpu->kvm, intid)) in vgic_v3_fold_lr_state()
66 kvm_notify_acked_irq(vcpu->kvm, 0, in vgic_v3_fold_lr_state()
67 intid - VGIC_NR_PRIVATE_IRQS); in vgic_v3_fold_lr_state()
73 raw_spin_lock(&irq->irq_lock); in vgic_v3_fold_lr_state()
76 deactivated = irq->active && !(val & ICH_LR_ACTIVE_BIT); in vgic_v3_fold_lr_state()
77 irq->active = !!(val & ICH_LR_ACTIVE_BIT); in vgic_v3_fold_lr_state()
79 if (irq->active && is_v2_sgi) in vgic_v3_fold_lr_state()
80 irq->active_source = cpuid; in vgic_v3_fold_lr_state()
83 if (irq->config == VGIC_CONFIG_EDGE && in vgic_v3_fold_lr_state()
85 irq->pending_latch = true; in vgic_v3_fold_lr_state()
88 irq->source |= (1 << cpuid); in vgic_v3_fold_lr_state()
94 if (irq->config == VGIC_CONFIG_LEVEL && !(val & ICH_LR_STATE)) in vgic_v3_fold_lr_state()
95 irq->pending_latch = false; in vgic_v3_fold_lr_state()
100 raw_spin_unlock(&irq->irq_lock); in vgic_v3_fold_lr_state()
101 vgic_put_irq(vcpu->kvm, irq); in vgic_v3_fold_lr_state()
104 cpuif->used_lrs = 0; in vgic_v3_fold_lr_state()
110 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_populate_lr()
111 u64 val = irq->intid; in vgic_v3_populate_lr()
114 is_v2_sgi = (vgic_irq_is_sgi(irq->intid) && in vgic_v3_populate_lr()
117 if (irq->active) { in vgic_v3_populate_lr()
120 val |= irq->active_source << GICH_LR_PHYSID_CPUID_SHIFT; in vgic_v3_populate_lr()
127 if (irq->hw && !vgic_irq_needs_resampling(irq)) { in vgic_v3_populate_lr()
129 val |= ((u64)irq->hwintid) << ICH_LR_PHYS_ID_SHIFT; in vgic_v3_populate_lr()
135 if (irq->active) in vgic_v3_populate_lr()
138 if (irq->config == VGIC_CONFIG_LEVEL) { in vgic_v3_populate_lr()
145 if (irq->active) in vgic_v3_populate_lr()
153 if (irq->config == VGIC_CONFIG_EDGE) in vgic_v3_populate_lr()
154 irq->pending_latch = false; in vgic_v3_populate_lr()
156 if (vgic_irq_is_sgi(irq->intid) && in vgic_v3_populate_lr()
158 u32 src = ffs(irq->source); in vgic_v3_populate_lr()
161 irq->intid)) in vgic_v3_populate_lr()
164 val |= (src - 1) << GICH_LR_PHYSID_CPUID_SHIFT; in vgic_v3_populate_lr()
165 irq->source &= ~(1 << (src - 1)); in vgic_v3_populate_lr()
166 if (irq->source) { in vgic_v3_populate_lr()
167 irq->pending_latch = true; in vgic_v3_populate_lr()
174 * Level-triggered mapped IRQs are special because we only observe in vgic_v3_populate_lr()
180 irq->line_level = false; in vgic_v3_populate_lr()
182 if (irq->group) in vgic_v3_populate_lr()
185 val |= (u64)irq->priority << ICH_LR_PRIORITY_SHIFT; in vgic_v3_populate_lr()
187 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = val; in vgic_v3_populate_lr()
192 vcpu->arch.vgic_cpu.vgic_v3.vgic_lr[lr] = 0; in vgic_v3_clear_lr()
197 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_set_vmcr()
198 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_set_vmcr()
202 vmcr = (vmcrp->ackctl << ICH_VMCR_ACK_CTL_SHIFT) & in vgic_v3_set_vmcr()
204 vmcr |= (vmcrp->fiqen << ICH_VMCR_FIQ_EN_SHIFT) & in vgic_v3_set_vmcr()
214 vmcr |= (vmcrp->cbpr << ICH_VMCR_CBPR_SHIFT) & ICH_VMCR_CBPR_MASK; in vgic_v3_set_vmcr()
215 vmcr |= (vmcrp->eoim << ICH_VMCR_EOIM_SHIFT) & ICH_VMCR_EOIM_MASK; in vgic_v3_set_vmcr()
216 vmcr |= (vmcrp->abpr << ICH_VMCR_BPR1_SHIFT) & ICH_VMCR_BPR1_MASK; in vgic_v3_set_vmcr()
217 vmcr |= (vmcrp->bpr << ICH_VMCR_BPR0_SHIFT) & ICH_VMCR_BPR0_MASK; in vgic_v3_set_vmcr()
218 vmcr |= (vmcrp->pmr << ICH_VMCR_PMR_SHIFT) & ICH_VMCR_PMR_MASK; in vgic_v3_set_vmcr()
219 vmcr |= (vmcrp->grpen0 << ICH_VMCR_ENG0_SHIFT) & ICH_VMCR_ENG0_MASK; in vgic_v3_set_vmcr()
220 vmcr |= (vmcrp->grpen1 << ICH_VMCR_ENG1_SHIFT) & ICH_VMCR_ENG1_MASK; in vgic_v3_set_vmcr()
222 cpu_if->vgic_vmcr = vmcr; in vgic_v3_set_vmcr()
227 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_get_vmcr()
228 u32 model = vcpu->kvm->arch.vgic.vgic_model; in vgic_v3_get_vmcr()
231 vmcr = cpu_if->vgic_vmcr; in vgic_v3_get_vmcr()
234 vmcrp->ackctl = (vmcr & ICH_VMCR_ACK_CTL_MASK) >> in vgic_v3_get_vmcr()
236 vmcrp->fiqen = (vmcr & ICH_VMCR_FIQ_EN_MASK) >> in vgic_v3_get_vmcr()
243 vmcrp->fiqen = 1; in vgic_v3_get_vmcr()
244 vmcrp->ackctl = 0; in vgic_v3_get_vmcr()
247 vmcrp->cbpr = (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; in vgic_v3_get_vmcr()
248 vmcrp->eoim = (vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT; in vgic_v3_get_vmcr()
249 vmcrp->abpr = (vmcr & ICH_VMCR_BPR1_MASK) >> ICH_VMCR_BPR1_SHIFT; in vgic_v3_get_vmcr()
250 vmcrp->bpr = (vmcr & ICH_VMCR_BPR0_MASK) >> ICH_VMCR_BPR0_SHIFT; in vgic_v3_get_vmcr()
251 vmcrp->pmr = (vmcr & ICH_VMCR_PMR_MASK) >> ICH_VMCR_PMR_SHIFT; in vgic_v3_get_vmcr()
252 vmcrp->grpen0 = (vmcr & ICH_VMCR_ENG0_MASK) >> ICH_VMCR_ENG0_SHIFT; in vgic_v3_get_vmcr()
253 vmcrp->grpen1 = (vmcr & ICH_VMCR_ENG1_MASK) >> ICH_VMCR_ENG1_SHIFT; in vgic_v3_get_vmcr()
263 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_enable()
270 vgic_v3->vgic_vmcr = 0; in vgic_v3_enable()
273 * If we are emulating a GICv3, we do it in an non-GICv2-compatible in vgic_v3_enable()
275 * Also, we don't support any form of IRQ/FIQ bypass. in vgic_v3_enable()
278 if (vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3) { in vgic_v3_enable()
279 vgic_v3->vgic_sre = (ICC_SRE_EL1_DIB | in vgic_v3_enable()
282 vcpu->arch.vgic_cpu.pendbaser = INITIAL_PENDBASER_VALUE; in vgic_v3_enable()
284 vgic_v3->vgic_sre = 0; in vgic_v3_enable()
287 vcpu->arch.vgic_cpu.num_id_bits = (kvm_vgic_global_state.ich_vtr_el2 & in vgic_v3_enable()
290 vcpu->arch.vgic_cpu.num_pri_bits = ((kvm_vgic_global_state.ich_vtr_el2 & in vgic_v3_enable()
295 vgic_v3->vgic_hcr = ICH_HCR_EN; in vgic_v3_enable()
300 struct vgic_v3_cpu_if *vgic_v3 = &vcpu->arch.vgic_cpu.vgic_v3; in vcpu_set_ich_hcr()
303 if (!kvm_has_gicv3(vcpu->kvm)) { in vcpu_set_ich_hcr()
304 vgic_v3->vgic_hcr |= ICH_HCR_TALL0 | ICH_HCR_TALL1 | ICH_HCR_TC; in vcpu_set_ich_hcr()
309 vgic_v3->vgic_hcr |= ICH_HCR_TALL0; in vcpu_set_ich_hcr()
311 vgic_v3->vgic_hcr |= ICH_HCR_TALL1; in vcpu_set_ich_hcr()
313 vgic_v3->vgic_hcr |= ICH_HCR_TC; in vcpu_set_ich_hcr()
315 vgic_v3->vgic_hcr |= ICH_HCR_TDIR; in vcpu_set_ich_hcr()
329 vcpu = irq->target_vcpu; in vgic_v3_lpi_sync_pending_status()
333 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); in vgic_v3_lpi_sync_pending_status()
335 byte_offset = irq->intid / BITS_PER_BYTE; in vgic_v3_lpi_sync_pending_status()
336 bit_nr = irq->intid % BITS_PER_BYTE; in vgic_v3_lpi_sync_pending_status()
345 raw_spin_lock_irqsave(&irq->irq_lock, flags); in vgic_v3_lpi_sync_pending_status()
346 if (irq->target_vcpu != vcpu) { in vgic_v3_lpi_sync_pending_status()
347 raw_spin_unlock_irqrestore(&irq->irq_lock, flags); in vgic_v3_lpi_sync_pending_status()
350 irq->pending_latch = status; in vgic_v3_lpi_sync_pending_status()
351 vgic_queue_irq_unlock(vcpu->kvm, irq, flags); in vgic_v3_lpi_sync_pending_status()
369 struct vgic_dist *dist = &kvm->arch.vgic; in unmap_all_vpes()
372 for (i = 0; i < dist->its_vm.nr_vpes; i++) in unmap_all_vpes()
373 free_irq(dist->its_vm.vpes[i]->irq, kvm_get_vcpu(kvm, i)); in unmap_all_vpes()
378 struct vgic_dist *dist = &kvm->arch.vgic; in map_all_vpes()
381 for (i = 0; i < dist->its_vm.nr_vpes; i++) in map_all_vpes()
383 dist->its_vm.vpes[i]->irq)); in map_all_vpes()
387 * vgic_v3_save_pending_tables - Save the pending tables into guest RAM
392 struct vgic_dist *dist = &kvm->arch.vgic; in vgic_v3_save_pending_tables()
396 unsigned long index; in vgic_v3_save_pending_tables() local
401 return -ENXIO; in vgic_v3_save_pending_tables()
413 xa_for_each(&dist->lpi_xa, index, irq) { in vgic_v3_save_pending_tables()
420 vcpu = irq->target_vcpu; in vgic_v3_save_pending_tables()
424 pendbase = GICR_PENDBASER_ADDRESS(vcpu->arch.vgic_cpu.pendbaser); in vgic_v3_save_pending_tables()
426 byte_offset = irq->intid / BITS_PER_BYTE; in vgic_v3_save_pending_tables()
427 bit_nr = irq->intid % BITS_PER_BYTE; in vgic_v3_save_pending_tables()
439 is_pending = irq->pending_latch; in vgic_v3_save_pending_tables()
441 if (irq->hw && vlpi_avail) in vgic_v3_save_pending_tables()
465 * vgic_v3_rdist_overlap - check if a region overlaps with any
476 struct vgic_dist *d = &kvm->arch.vgic; in vgic_v3_rdist_overlap()
479 list_for_each_entry(rdreg, &d->rd_regions, list) { in vgic_v3_rdist_overlap()
480 if ((base + size > rdreg->base) && in vgic_v3_rdist_overlap()
481 (base < rdreg->base + vgic_v3_rd_region_size(kvm, rdreg))) in vgic_v3_rdist_overlap()
493 struct vgic_dist *d = &kvm->arch.vgic; in vgic_v3_check_base()
496 if (!IS_VGIC_ADDR_UNDEF(d->vgic_dist_base) && in vgic_v3_check_base()
497 d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE < d->vgic_dist_base) in vgic_v3_check_base()
500 list_for_each_entry(rdreg, &d->rd_regions, list) { in vgic_v3_check_base()
504 rdreg->base, SZ_64K, sz)) in vgic_v3_check_base()
508 if (IS_VGIC_ADDR_UNDEF(d->vgic_dist_base)) in vgic_v3_check_base()
511 return !vgic_v3_rdist_overlap(kvm, d->vgic_dist_base, in vgic_v3_check_base()
516 * vgic_v3_rdist_free_slot - Look up registered rdist regions and identify one
522 * Stride between redistributors is 0 and regions are filled in the index order.
539 u32 index) in vgic_v3_rdist_region_from_index() argument
541 struct list_head *rd_regions = &kvm->arch.vgic.rd_regions; in vgic_v3_rdist_region_from_index()
545 if (rdreg->index == index) in vgic_v3_rdist_region_from_index()
554 struct vgic_dist *dist = &kvm->arch.vgic; in vgic_v3_map_resources()
559 struct vgic_cpu *vgic_cpu = &vcpu->arch.vgic_cpu; in vgic_v3_map_resources()
561 if (IS_VGIC_ADDR_UNDEF(vgic_cpu->rd_iodev.base_addr)) { in vgic_v3_map_resources()
563 return -ENXIO; in vgic_v3_map_resources()
567 if (IS_VGIC_ADDR_UNDEF(dist->vgic_dist_base)) { in vgic_v3_map_resources()
569 return -ENXIO; in vgic_v3_map_resources()
574 return -EINVAL; in vgic_v3_map_resources()
582 return -EBUSY; in vgic_v3_map_resources()
597 early_param("kvm-arm.vgic_v3_group0_trap", early_group0_trap_cfg);
603 early_param("kvm-arm.vgic_v3_group1_trap", early_group1_trap_cfg);
609 early_param("kvm-arm.vgic_v3_common_trap", early_common_trap_cfg);
615 early_param("kvm-arm.vgic_v4_enable", early_gicv4_enable);
640 * vgic_v3_probe - probe for a VGICv3 compatible interrupt controller
664 if (info->has_v4) { in vgic_v3_probe()
666 kvm_vgic_global_state.has_gicv4_1 = info->has_v4_1 && gicv4_enable; in vgic_v3_probe()
674 if (!info->vcpu.start) { in vgic_v3_probe()
678 } else if (!PAGE_ALIGNED(info->vcpu.start)) { in vgic_v3_probe()
680 (unsigned long long)info->vcpu.start); in vgic_v3_probe()
682 kvm_vgic_global_state.vcpu_base = info->vcpu.start; in vgic_v3_probe()
689 kvm_info("vgic-v2@%llx\n", info->vcpu.start); in vgic_v3_probe()
736 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_load()
749 struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3; in vgic_v3_put()