951 		v |= masks->mask[sr].res1;  in kvm_vcpu_apply_reg_masks()
957 static __always_inline void set_sysreg_masks(struct kvm *kvm, int sr, u64 res0, u64 res1)  in set_sysreg_masks()  argument
966 	kvm->arch.sysreg_masks->mask[i].res1 = res1;  in set_sysreg_masks()
972 	u64 res0, res1;  in kvm_init_nv_sysregs()  local
987 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
992 	set_sysreg_masks(kvm, VTTBR_EL2, res0, res1);  in kvm_init_nv_sysregs()
996 	res1 = BIT(31);  in kvm_init_nv_sysregs()
997 	set_sysreg_masks(kvm, VTCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1001 	res1 = BIT(31);  in kvm_init_nv_sysregs()
1002 	set_sysreg_masks(kvm, VMPIDR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1006 	res1 = HCR_RW;  in kvm_init_nv_sysregs()
1038 		res1 |= HCR_E2H;  in kvm_init_nv_sysregs()
1039 	set_sysreg_masks(kvm, HCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1043 	res1 = HCRX_EL2_RES1;  in kvm_init_nv_sysregs()
1081 	set_sysreg_masks(kvm, HCRX_EL2, res0, res1);  in kvm_init_nv_sysregs()
1084 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1121 	set_sysreg_masks(kvm, HFGRTR_EL2, res0 | __HFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1122 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | __HFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1125 	res0 = res1 = 0;  in kvm_init_nv_sysregs()
1160 	set_sysreg_masks(kvm, HDFGRTR_EL2, res0 | HDFGRTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1169 	set_sysreg_masks(kvm, HFGWTR_EL2, res0 | HDFGWTR_EL2_RES0, res1);  in kvm_init_nv_sysregs()
1173 	res1 = HFGITR_EL2_RES1;  in kvm_init_nv_sysregs()
1203 	set_sysreg_masks(kvm, HFGITR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1207 	res1 = HAFGRTR_EL2_RES1;  in kvm_init_nv_sysregs()
1209 		res0 |= ~(res0 | res1);  in kvm_init_nv_sysregs()
1210 	set_sysreg_masks(kvm, HAFGRTR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1214 	res1 = TCR2_EL2_RES1;  in kvm_init_nv_sysregs()
1232 	set_sysreg_masks(kvm, TCR2_EL2, res0, res1);  in kvm_init_nv_sysregs()
1236 	res1 = SCTLR_EL1_RES1;  in kvm_init_nv_sysregs()
1239 	set_sysreg_masks(kvm, SCTLR_EL1, res0, res1);  in kvm_init_nv_sysregs()
1243 	res1 = MDCR_EL2_RES1;  in kvm_init_nv_sysregs()
1276 	set_sysreg_masks(kvm, MDCR_EL2, res0, res1);  in kvm_init_nv_sysregs()
1280 	res1 = 0;  in kvm_init_nv_sysregs()
1291 	set_sysreg_masks(kvm, CNTHCTL_EL2, res0, res1);  in kvm_init_nv_sysregs()