75  * This performs the exception entry at a given EL (@target_mode), stashing PC
80  * When an exception is taken, most PSTATE fields are left unchanged in the
139 	// PSTATE.UAO is set to zero upon any exception to AArch64  in enter_exception64()
149 	// PSTATE.SS is set to zero upon any exception to AArch64  in enter_exception64()
152 	// PSTATE.IL is set to zero upon any exception to AArch64  in enter_exception64()
155 	// PSTATE.SSBS is set to SCTLR_ELx.DSSBS upon any exception to AArch64  in enter_exception64()
160 	// PSTATE.BTYPE is set to zero upon any exception to AArch64  in enter_exception64()
175  * When an exception is taken, most CPSR fields are left unchanged in the
206 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
212 	// CPSR.SSBS is set to SCTLR.DSSBS upon any exception  in get_except32_cpsr()
226 	// CPSR.IL is set to zero upon any exception  in get_except32_cpsr()
231 	// CPSR.IT[7:0] are set to zero upon any exception  in get_except32_cpsr()
234 	// CPSR.E is set to SCTLR.EE upon any exception  in get_except32_cpsr()
240 	// CPSR.A is unchanged upon an exception to Undefined, Supervisor  in get_except32_cpsr()
241 	// CPSR.A is set upon an exception to other modes  in get_except32_cpsr()
248 	// CPSR.I is set upon any exception  in get_except32_cpsr()
253 	// CPSR.F is set upon an exception to FIQ  in get_except32_cpsr()
254 	// CPSR.F is unchanged upon an exception to other modes  in get_except32_cpsr()
261 	// CPSR.T is set to SCTLR.TE upon any exception  in get_except32_cpsr()
310 	/* Branch to exception vector */  in enter_exception32()
362  * Adjust the guest PC (and potentially exception state) depending on