75  * This performs the exception entry at a given EL (@target_mode), stashing PC
77  * The EL passed to this function *must* be a non-secure, privileged mode with
85  * For the SPSR_ELx layout for AArch64, see ARM DDI 0487E.a page C5-429.
86  * For the SPSR_ELx layout for AArch32, see ARM DDI 0487E.a page C5-426.
140 	// See ARM DDI 0487E.a, page D5-2579.  in enter_exception64()
144 	// See ARM DDI 0487E.a, page D5-2578.  in enter_exception64()
150 	// See ARM DDI 0487E.a, page D2-2452.  in enter_exception64()
153 	// See ARM DDI 0487E.a, page D1-2306.  in enter_exception64()
156 	// See ARM DDI 0487E.a, page D13-3258  in enter_exception64()
161 	// See ARM DDI 0487E.a, pages D1-2293 to D1-2294.  in enter_exception64()
184  * - ARM DDI 0487E.a, page G8-6264
187  * - ARM DDI 0487E.a, page C5-426
207 	// See ARM DDI 0487E.a, section G1.12.3  in get_except32_cpsr()
213 	// See ARM DDI 0487E.a, page G8-6244  in get_except32_cpsr()
219 	// See ARM DDI 0487E.a, page G8-6246  in get_except32_cpsr()
227 	// See ARM DDI 0487E.a, page G1-5527  in get_except32_cpsr()
235 	// See ARM DDI 0487E.a, page G8-6245  in get_except32_cpsr()
240 	// CPSR.A is unchanged upon an exception to Undefined, Supervisor  in get_except32_cpsr()
241 	// CPSR.A is set upon an exception to other modes  in get_except32_cpsr()
242 	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516  in get_except32_cpsr()
249 	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516  in get_except32_cpsr()
255 	// See ARM DDI 0487E.a, pages G1-5515 to G1-5516  in get_except32_cpsr()
262 	// See ARM DDI 0487E.a, page G8-5514  in get_except32_cpsr()