Lines Matching +full:fiq +full:- +full:device
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
10 #include <linux/arm-smccc.h>
16 #include <asm/asm-offsets.h>
30 #include <asm/asm-uaccess.h>
65 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
67 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
68 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
90 * after panic() re-enables interrupts.
94 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
95 b.ne __bad_stack // no? -> bad stack pointer
106 .set .Lalias\@, TRAMP_VALIAS + \sym - .entry.tramp.text
113 * This macro corrupts x0-x3. It is the caller's duty to save/restore
242 * Enable IA for in-kernel PAC if the task had it disabled. Although
244 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
266 * Any non-self-synchronizing system register updates required for
330 * x20 - ICC_PMR_EL1
331 * x21 - aborted SP
332 * x22 - aborted PC
333 * x23 - aborted PSTATE
392 * IA was enabled for in-kernel PAC. Disable it now if needed, or
393 * alternatively install the user's IA. All other per-task keys and
459 /* Ensure any device/NC reads complete */
492 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
503 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
524 kernel_ventry 1, t, 64, fiq // FIQ EL1t
529 kernel_ventry 1, h, 64, fiq // FIQ EL1h
532 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
533 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
534 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
535 kernel_ventry 0, t, 64, error // Error 64-bit EL0
537 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
538 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
539 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
540 kernel_ventry 0, t, 32, error // Error 32-bit EL0
592 entry_handler 1, t, 64, fiq
597 entry_handler 1, h, 64, fiq
602 entry_handler 0, t, 64, fiq
607 entry_handler 0, t, 32, fiq
615 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
637 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
674 * 47 bits of the address space we can sign-extend bit 47 and avoid an
712 * enter the full-fat kernel vectors.
721 prfm plil1strm, [x30, #(1b - \vector_start)]
739 add x30, x30, #(1b - \vector_start + 4)
790 kernel_ventry 1, t, 64, fiq // FIQ EL1h
795 kernel_ventry 1, h, 64, fiq // FIQ EL1h
820 * Register switch for AArch64. The callee-saved registers need to be saved
831 stp x19, x20, [x8], #16 // store callee-saved registers
839 ldp x19, x20, [x8], #16 // restore callee-saved registers
884 stp x29, x30, [sp, #-16]!
974 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
975 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
998 /* Store the registered-event for crash_smp_send_stop() */
1031 * We may have interrupted userspace, or a guest, or exit-from or
1032 * return-to either of these. We can't trust sp_el0, restore it.
1045 stp x29, x4, [sp, #-16]!
1071 /* Clear the registered-event seen by crash_smp_send_stop() */
1096 // Exit will stomp x0-x17, PSTATE, ELR_ELx, and SPSR_ELx.