Lines Matching +full:0 +full:x21
34 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
42 .if \el == 0
66 tbnz x0, #THREAD_SHIFT, 0f
71 0:
127 nop // Patched to SMC/HVC #0
200 .if \el == 0
206 stp x0, x1, [sp, #16 * 0]
216 stp x20, x21, [sp, #16 * 10]
222 .if \el == 0
224 mrs x21, sp_el0
280 add x21, sp, #PT_REGS_SIZE
282 .endif /* \el == 0 */
285 stp lr, x21, [sp, #S_LR]
292 .if \el == 0
309 .if \el == 0
331 * x21 - aborted SP
338 .if \el != 0
358 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
366 .if \el == 0
411 apply_ssbd 0, x0, x1
414 msr elr_el1, x21 // set up the return data
416 ldp x0, x1, [sp, #16 * 0]
426 ldp x20, x21, [sp, #16 * 10]
432 .if \el == 0
452 .if \el == 0
477 mrs x21, ttbr0_el1
478 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
483 __uaccess_ttbr0_disable x21
494 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
532 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
533 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
534 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
535 kernel_ventry 0, t, 64, error // Error 64-bit EL0
537 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
538 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
539 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
540 kernel_ventry 0, t, 32, error // Error 32-bit EL0
579 .if \el == 0
600 entry_handler 0, t, 64, sync
601 entry_handler 0, t, 64, irq
602 entry_handler 0, t, 64, fiq
603 entry_handler 0, t, 64, error
605 entry_handler 0, t, 32, sync
606 entry_handler 0, t, 32, irq
607 entry_handler 0, t, 32, fiq
608 entry_handler 0, t, 32, error
620 kernel_exit 0
675 * instruction to load the upper 16 bits (which must be 0xFFFF).
683 #define BHB_MITIGATION_NONE 0
746 .space 0x400
799 tramp_ventry .Lvector_start\@, 64, 0, \bhb
802 tramp_ventry .Lvector_start\@, 32, 0, \bhb
832 stp x21, x22, [x8], #16
840 ldp x21, x22, [x8], #16
913 smc #0
915 99: hvc #0
988 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
1039 and x0, x3, #0xc