Lines Matching +full:5 +full:- +full:7
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
36 #define Op2_shift 5
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
112 /* Register-based PAN access, for save/restore purposes */
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
120 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
121 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
122 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
123 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
124 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
125 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
126 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
130 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
131 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
132 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1)
134 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
135 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
136 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
138 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1)
139 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3)
140 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5)
142 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1)
144 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1)
145 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3)
146 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5)
148 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1)
149 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3)
150 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5)
152 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1)
153 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3)
154 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
167 #include "asm/sysreg-defs.h"
178 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
180 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
196 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
213 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3)))
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
215 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
222 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6)
223 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
228 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6)
229 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
257 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2)
258 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2)
259 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3)
271 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1)
279 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
283 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
306 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
307 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
308 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
310 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
311 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
312 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
313 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
314 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
315 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
316 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
317 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
318 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
319 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
320 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
321 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
322 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
323 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
324 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
326 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
338 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16))
341 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7)
369 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
399 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
401 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
407 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
409 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
411 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
415 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
426 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
435 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
437 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
446 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
455 * n: 0-15
461 * n: 0-15
464 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
465 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
466 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
467 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
479 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
504 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7)
507 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
516 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
533 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
534 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
535 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
536 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
537 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
538 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
539 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
564 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
569 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
570 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
578 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
580 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
588 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
590 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
594 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
613 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
614 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
615 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
616 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
617 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
618 #define SYS_TRFCR_EL12 sys_reg(3, 5, 1, 2, 1)
619 #define SYS_SMCR_EL12 sys_reg(3, 5, 1, 2, 6)
620 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
621 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
622 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
623 #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
624 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
625 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
626 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
627 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1)
628 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
629 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
630 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
631 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
632 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
633 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
634 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
635 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
636 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
637 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
638 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
639 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1)
640 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2)
641 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
642 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1)
643 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2)
649 #define AT_CRn 7
661 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
663 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
675 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
676 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
677 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
678 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
679 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
680 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
681 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
682 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
688 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
689 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
692 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
693 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
698 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
699 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
700 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
701 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
702 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
703 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
706 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
707 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
708 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
709 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
710 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
711 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
712 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
713 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
718 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
719 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
722 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
723 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
728 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
729 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
730 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
731 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
732 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
733 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
736 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
737 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
738 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
739 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
740 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
741 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
742 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
743 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
746 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
751 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
754 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
758 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
765 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
767 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
768 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
769 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
771 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
772 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
773 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
774 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
775 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
776 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
779 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
784 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
787 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
791 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
798 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
800 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
801 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
802 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
804 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
805 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
806 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
807 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
808 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
809 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
812 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
813 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
814 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
815 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
817 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
818 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5)
819 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
820 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5)
821 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6)
822 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7)
852 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
961 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
993 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1027 #define ICH_VMCR_BPR1_MASK (7 << ICH_VMCR_BPR1_SHIFT)
1029 #define ICH_VMCR_BPR0_MASK (7 << ICH_VMCR_BPR0_SHIFT)
1039 #define ICH_VTR_PRI_BITS_MASK (7 << ICH_VTR_PRI_BITS_SHIFT)
1041 #define ICH_VTR_ID_BITS_MASK (7 << ICH_VTR_ID_BITS_SHIFT)
1197 * set mask are set. Other bits are left as-is.