Lines Matching +full:0 +full:- +full:4
1 /* SPDX-License-Identifier: GPL-2.0-only */
14 #include <linux/kasan-tags.h>
16 #include <asm/gpr-num.h>
22 * [20-19] : Op0
23 * [18-16] : Op1
24 * [15-12] : CRn
25 * [11-8] : CRm
26 * [7-5] : Op2
29 #define Op0_mask 0x3
31 #define Op1_mask 0x7
33 #define CRn_mask 0xf
35 #define CRm_mask 0xf
37 #define Op2_mask 0x7
67 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
68 (((x) << 8) & 0x00ff0000) | \
69 (((x) >> 8) & 0x0000ff00) | \
70 (((x) >> 24) & 0x000000ff))
83 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints,
86 * Op0 = 0, CRn = 4
89 * Rt = 0x1f
93 #define SET_PSTATE(x, r) __emit_inst(0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift))
95 #define PSTATE_PAN pstate_field(0, 4)
96 #define PSTATE_UAO pstate_field(0, 3)
99 #define PSTATE_TCO pstate_field(3, 4)
112 /* Register-based PAN access, for save/restore purposes */
113 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3)
116 __emit_inst(0xd5000000 | sys_insn(0, 3, 3, (CRm), (op2)) | ((Rt) & 0x1f))
118 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 7, 31)
120 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
121 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4)
122 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6)
123 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
124 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4)
125 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6)
126 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
127 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4)
128 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6)
130 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0)
131 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0)
134 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1)
135 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3)
136 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5)
157 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1)
158 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3)
159 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4)
167 #include "asm/sysreg-defs.h"
173 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3)
174 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3)
175 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3)
177 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
178 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
179 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
180 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
181 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
183 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
184 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0))
185 #define OSLSR_EL1_OSLM_NI 0
189 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
190 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
191 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
192 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
193 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
194 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
195 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
196 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
197 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
198 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
200 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0))
201 #define SYS_BRBINFINJ_EL1 sys_reg(2, 1, 9, 1, 0)
206 #define SYS_BRBTS_EL1 sys_reg(2, 1, 9, 0, 2)
208 #define SYS_BRBCR_EL1 sys_reg(2, 1, 9, 0, 0)
209 #define SYS_BRBFCR_EL1 sys_reg(2, 1, 9, 0, 1)
210 #define SYS_BRBIDR0_EL1 sys_reg(2, 1, 9, 2, 0)
212 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3)
214 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3)))
216 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0)
217 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0)
218 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0)
219 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2)
221 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0)
224 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5)
225 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5)
226 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5)
227 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0)
230 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0)
231 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0)
232 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4)
233 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7)
234 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6)
235 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6)
236 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6)
237 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6)
238 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7)
239 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7)
240 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7)
241 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7)
242 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7)
243 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7)
244 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7)
245 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6)
246 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6)
247 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7)
248 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1)
249 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4)
250 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0)
251 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1)
252 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4)))
253 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0)
254 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4)
255 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4)
256 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4)
260 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0)
261 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0)
262 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0)
263 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1)
264 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0)
265 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2)
266 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2)
267 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2)
268 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2)
274 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4)
276 #define SYS_BRBCR_EL2 sys_reg(2, 4, 9, 0, 0)
278 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
279 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
280 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
282 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
283 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5)
284 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6)
286 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
288 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0)
289 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1)
290 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2)
291 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3)
293 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0)
294 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1)
295 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2)
296 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3)
298 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0)
299 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1)
301 #define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0)
302 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1)
304 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
306 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
307 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
308 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
310 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0)
311 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1)
312 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0)
313 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1)
314 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2)
315 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3)
316 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4)
317 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5)
318 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6)
319 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0)
320 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1)
321 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2)
322 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3)
323 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0)
324 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1)
326 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
328 #define SYS_PAR_EL1_F BIT(0)
340 /* When PAR_EL1.F == 0 */
352 BIT_ULL(6) | BIT_ULL(4) | BIT_ULL(2) | BIT_ULL(0))
365 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL
369 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0)
370 #define TRBSR_EL1_BSC_SHIFT 0
372 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
373 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
375 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6)
377 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
378 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
380 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
381 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1)
383 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
384 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
385 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
386 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
387 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
388 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
392 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
393 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
397 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
398 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
399 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
400 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6)
401 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7)
402 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
403 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
404 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
405 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
406 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
407 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
408 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
409 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
411 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5)
413 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
415 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
417 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0)
418 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1)
420 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
424 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
427 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
430 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
433 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
434 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
435 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5)
437 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7)
439 /* Definitions for system register interface to AMU for ARMv8.4 onwards */
441 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
445 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
447 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
451 * Group 0 of activity monitors (architected):
453 * Counter: 11 011 1101 010:n<3> n<2:0>
454 * Type: 11 011 1101 011:n<3> n<2:0>
455 * n: 0-15
459 * Counter: 11 011 1101 110:n<3> n<2:0>
460 * Type: 11 011 1101 111:n<3> n<2:0>
461 * n: 0-15
464 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
470 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
475 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
477 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1)
478 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2)
479 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5)
480 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6)
482 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
486 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0)
490 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0)
491 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1)
492 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0)
493 #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0)
494 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0)
495 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0)
496 #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0)
498 #define __PMEV_op2(n) ((n) & 0x7)
499 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
501 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
506 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0)
507 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5)
509 #define SYS_SCTLR_EL2 sys_reg(3, 4, 1, 0, 0)
510 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1)
511 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3)
512 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0)
513 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1)
514 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2)
515 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3)
516 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7)
518 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0)
519 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1)
520 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2)
521 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0)
522 #define SYS_VTCR_EL2 sys_reg(3, 4, 2, 1, 2)
524 #define SYS_VNCR_EL2 sys_reg(3, 4, 2, 2, 0)
525 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6)
526 #define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0)
527 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1)
528 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0)
529 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0)
530 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1)
531 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2)
532 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3)
533 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
534 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0)
535 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1)
536 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0)
537 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3)
538 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
539 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0)
541 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0)
542 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4)
544 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0)
545 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0)
547 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0)
548 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1)
549 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2)
550 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1)
551 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
552 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
557 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
558 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
563 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
564 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
565 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
566 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
567 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
568 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
569 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5)
570 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
572 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
573 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
577 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
582 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
583 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
587 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
592 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1)
593 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2)
594 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7)
596 #define __AMEV_op2(m) (m & 0x7)
597 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3))
598 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m))
600 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m))
603 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3)
604 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0)
605 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0)
606 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1)
607 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2)
608 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0)
609 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1)
610 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2)
613 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0)
614 #define SYS_SCTLR_EL12 sys_reg(3, 5, 1, 0, 0)
615 #define SYS_CPACR_EL12 sys_reg(3, 5, 1, 0, 2)
616 #define SYS_SCTLR2_EL12 sys_reg(3, 5, 1, 0, 3)
617 #define SYS_ZCR_EL12 sys_reg(3, 5, 1, 2, 0)
620 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0)
621 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1)
622 #define SYS_TCR_EL12 sys_reg(3, 5, 2, 0, 2)
623 #define SYS_TCR2_EL12 sys_reg(3, 5, 2, 0, 3)
624 #define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0)
625 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1)
626 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0)
628 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0)
629 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0)
630 #define SYS_FAR_EL12 sys_reg(3, 5, 6, 0, 0)
631 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0)
632 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0)
633 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0)
634 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0)
635 #define SYS_CONTEXTIDR_EL12 sys_reg(3, 5, 13, 0, 1)
636 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7)
637 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0)
638 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0)
641 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0)
645 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0)
651 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0)
652 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1)
653 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2)
654 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3)
655 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0)
656 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1)
657 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2)
658 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0)
659 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1)
660 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4)
661 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5)
662 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6)
663 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7)
664 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2)
669 #define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */
670 #define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */
675 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */
676 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */
677 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */
678 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */
679 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */
680 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */
681 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */
682 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */
684 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
685 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
686 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
687 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
688 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
689 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
690 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
691 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
692 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
693 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
694 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
695 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
696 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
697 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
698 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
699 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
700 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
701 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
702 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
703 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
704 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
705 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
706 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
707 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
708 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
709 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
710 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
711 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
712 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
713 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
714 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
715 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
716 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
717 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
718 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
719 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
720 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
721 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
722 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
723 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
724 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
725 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
726 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
727 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
728 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
729 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
730 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
731 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
732 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
733 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
734 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
735 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
736 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
737 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
738 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
739 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
740 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
741 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
742 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
743 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
744 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
745 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
746 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
747 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
748 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
749 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
750 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
751 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
752 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
753 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
754 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
755 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
756 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
757 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
758 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
759 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
760 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
761 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
762 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
763 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
764 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
765 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
766 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
767 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
768 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
769 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
770 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
771 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
772 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
773 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
774 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
775 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
776 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
777 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
778 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
779 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
780 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
781 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
782 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
783 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
784 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
785 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
786 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
787 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
788 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
789 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
790 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
791 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
792 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
793 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
794 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
795 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
796 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
797 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
798 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
799 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
800 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
801 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
802 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
803 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
804 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
805 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
806 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
807 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
808 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
809 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
812 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4)
813 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5)
814 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6)
815 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0)
817 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4)
819 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4)
849 #define SCTLR_ELx_M (BIT(0))
852 #define SCTLR_EL2_RES1 ((BIT(4)) | (BIT(5)) | (BIT(11)) | (BIT(16)) | \
860 #define ENDIAN_SET_EL2 0
875 #define ENDIAN_SET_EL1 0
892 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00)
893 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04)
894 #define MAIR_ATTR_NORMAL_NC UL(0x44)
895 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0)
896 #define MAIR_ATTR_NORMAL UL(0xff)
897 #define MAIR_ATTR_MASK UL(0xff)
903 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0
905 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7
906 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
907 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
908 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
910 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
914 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0
915 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1
916 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2
917 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3
918 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7
956 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL
961 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF.
963 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf)
964 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf)
974 #define SYS_RGSR_EL1_TAG_MASK 0xfUL
976 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL
979 #define SYS_TFSR_EL1_TF0_SHIFT 0
984 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
989 #define ICH_MISR_EOI (1 << 0)
993 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1)
1002 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT)
1004 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT)
1007 #define ICH_HCR_EN (1 << 0)
1015 #define ICH_HCR_EOIcount_MASK (0x1f << ICH_HCR_EOIcount_SHIFT)
1022 #define ICH_VMCR_CBPR_SHIFT 4
1031 #define ICH_VMCR_PMR_MASK (0xffUL << ICH_VMCR_PMR_SHIFT)
1032 #define ICH_VMCR_ENG0_SHIFT 0
1053 #define PIE_NONE_O UL(0x0)
1054 #define PIE_R_O UL(0x1)
1055 #define PIE_X_O UL(0x2)
1056 #define PIE_RX_O UL(0x3)
1057 #define PIE_RW_O UL(0x5)
1058 #define PIE_RWnX_O UL(0x6)
1059 #define PIE_RWX_O UL(0x7)
1060 #define PIE_R UL(0x8)
1061 #define PIE_GCS UL(0x9)
1062 #define PIE_RX UL(0xa)
1063 #define PIE_RW UL(0xc)
1064 #define PIE_RWX UL(0xe)
1066 #define PIRx_ELx_PERM(idx, perm) ((perm) << ((idx) * 4))
1071 #define POE_NONE UL(0x0)
1072 #define POE_R UL(0x1)
1073 #define POE_X UL(0x2)
1074 #define POE_RX UL(0x3)
1075 #define POE_W UL(0x4)
1076 #define POE_RW UL(0x5)
1077 #define POE_XW UL(0x6)
1078 #define POE_RXW UL(0x7)
1079 #define POE_MASK UL(0xf)
1093 #define GCS_CAP_TOKEN_MASK GENMASK(11, 0)
1094 #define GCS_CAP_TOKEN_SHIFT 0
1098 #define GCS_CAP_VALID_TOKEN 0x1
1099 #define GCS_CAP_IN_PROGRESS_TOKEN 0x5
1104 #define ARM64_FEATURE_FIELD_BITS 4
1112 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt))
1116 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt))
1129 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \
1135 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \
1160 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
1172 } while (0)
1185 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \
1193 } while (0)
1197 * set mask are set. Other bits are left as-is.
1204 } while (0)
1211 } while (0)