Lines Matching +full:fiq +full:- +full:based
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2012,2013 - ARM Ltd
151 * We configure the Stage-2 page tables to always restrict the IPA space to be
170 * -----------------------------------------
172 * ------------------------------------------
173 * | Level: 0 | 2 | - |
174 * ------------------------------------------
176 * ------------------------------------------
178 * ------------------------------------------
179 * | Level: 3 | - | 0 |
180 * ------------------------------------------
184 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level
191 * Entry_Level = 4 - Number_of_levels.
212 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
214 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE)
219 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK))
222 * ARM VMSAv8-64 defines an algorithm for finding the translation table
226 * addresses for each level, based on PAGE_SIZE, entry level
232 * depending on the T0SZ, the value of "x" is defined based on a
238 * x = Magic_N - T0SZ
243 * --------------------------------------------
245 * --------------------------------------------
246 * | Level: 0 (4 levels) | 28 | - | - |
247 * --------------------------------------------
249 * --------------------------------------------
251 * --------------------------------------------
252 * | Level: 3 (1 level) | - | 53 | 51 |
253 * --------------------------------------------
257 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels)
259 * where Number_of_levels = (4 - Level). We are only interested in the
262 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows:
264 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT)
265 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels)
271 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another
274 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT)
275 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3
279 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n
284 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3)))
288 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
371 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12]
372 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12]
379 (((par) & GENMASK_ULL(52 - 1, 12)) >> 8)
402 { PSR_AA32_MODE_USR, "32-bit USR" }, \
403 { PSR_AA32_MODE_FIQ, "32-bit FIQ" }, \
404 { PSR_AA32_MODE_IRQ, "32-bit IRQ" }, \
405 { PSR_AA32_MODE_SVC, "32-bit SVC" }, \
406 { PSR_AA32_MODE_ABT, "32-bit ABT" }, \
407 { PSR_AA32_MODE_HYP, "32-bit HYP" }, \
408 { PSR_AA32_MODE_UND, "32-bit UND" }, \
409 { PSR_AA32_MODE_SYS, "32-bit SYS" }