Lines Matching +full:non +full:- +full:inclusive
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 1999-2002 Russell King.
26 * Start addresses are inclusive and end addresses are exclusive; start
29 * See Documentation/core-api/cachetlb.rst for more information. Please note that
30 * the implementation assumes non-aliasing VIPT D-cache and (aliasing)
31 * VIPT I-cache.
34 * - start - virtual start address (inclusive)
35 * - end - virtual end address (exclusive)
39 * Ensure coherency between the I-cache and the D-cache region to
44 * Ensure coherency between the I-cache and the D-cache region to
50 * Invalidate I-cache region to the Point of Unification.
54 * Clean and invalidate D-cache region to the Point of Coherency.
58 * Invalidate D-cache region to the Point of Coherency.
62 * Clean D-cache region to the Point of Coherency.
66 * Clean D-cache region to the Point of Persistence.
70 * Clean D-cache region to the Point of Unification.
96 * turns out, KGDB uses IPIs to round-up the secondary CPUs during in flush_icache_range()
98 * In which case, add a KGDB-specific bodge and return early. in flush_icache_range()
118 * cache page at virtual address page->virtual.
142 #include <asm-generic/cacheflush.h>