Lines Matching +full:0 +full:x875
31 bootscr-address = /bits/ 64 <0x20000000>;
37 #size-cells = <0>;
39 cpu0: cpu@0 {
45 reg = <0x0>;
55 reg = <0x1>;
66 reg = <0x2>;
77 reg = <0x3>;
92 CPU_SLEEP_0: cpu-sleep-0 {
94 arm,psci-suspend-param = <0x40000000>;
135 reg = <0x0 0x3ed00000 0x0 0x40000>;
140 reg = <0x0 0x3ef00000 0x0 0x40000>;
149 xlnx,ipi-id = <0>;
157 reg = <0x0 0xff9905c0 0x0 0x20>,
158 <0x0 0xff9905e0 0x0 0x20>,
159 <0x0 0xff990e80 0x0 0x20>,
160 <0x0 0xff990ea0 0x0 0x20>;
211 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
222 soc_revision: soc-revision@0 {
223 reg = <0x0 0x4>;
227 reg = <0xc 0xc>;
230 reg = <0x20 0x4>;
233 reg = <0x24 0x4>;
236 reg = <0x28 0x4>;
239 reg = <0x2c 0x4>;
242 reg = <0x30 0x4>;
245 reg = <0x34 0x4>;
248 reg = <0x38 0x4>;
251 reg = <0x3c 0x4>;
254 reg = <0x40 0x4>;
257 reg = <0x50 0x4>;
260 reg = <0x54 0x4>;
263 reg = <0x58 0x4>;
266 reg = <0x5c 0x4>;
269 reg = <0x60 0x20>;
272 reg = <0xa0 0x30>;
275 reg = <0xd0 0x30>;
278 reg = <0x100 0x7F>;
334 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
335 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
336 <0x0 0x10000 0x0 0xffe10000 0x0 0x10000>,
337 <0x0 0x30000 0x0 0xffe30000 0x0 0x10000>;
339 r5f@0 {
341 reg = <0x0 0x0 0x0 0x10000>,
342 <0x0 0x20000 0x0 0x10000>,
343 <0x0 0x10000 0x0 0x10000>,
344 <0x0 0x30000 0x0 0x10000>;
356 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
368 xlnx,cluster-mode = <0>;
369 xlnx,tcm-mode = <0>;
374 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x10000>,
375 <0x0 0x20000 0x0 0xffe20000 0x0 0x10000>,
376 <0x1 0x0 0x0 0xffe90000 0x0 0x10000>,
377 <0x1 0x20000 0x0 0xffeb0000 0x0 0x10000>;
379 r5f@0 {
381 reg = <0x0 0x0 0x0 0x10000>, <0x0 0x20000 0x0 0x10000>;
391 reg = <0x1 0x0 0x0 0x10000>, <0x1 0x20000 0x0 0x10000>;
402 io-channels = <&xilinx_ams 0>, <&xilinx_ams 1>, <&xilinx_ams 2>,
417 #thermal-sensor-cells = <0>;
424 #thermal-sensor-cells = <0>;
431 #thermal-sensor-cells = <0>;
506 reg = <0x0 0xff060000 0x0 0x1000>;
509 tx-fifo-depth = <0x40>;
510 rx-fifo-depth = <0x40>;
519 reg = <0x0 0xff070000 0x0 0x1000>;
522 tx-fifo-depth = <0x40>;
523 rx-fifo-depth = <0x40>;
531 reg = <0x0 0xfd6e0000 0x0 0x9000>;
532 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
538 reg = <0x9000 0x5000>;
550 reg = <0x0 0xfec10000 0x0 0x1000>;
557 reg = <0x0 0xfed10000 0x0 0x1000>;
564 reg = <0x0 0xfee10000 0x0 0x1000>;
571 reg = <0x0 0xfef10000 0x0 0x1000>;
580 reg = <0x0 0xfd500000 0x0 0x1000>;
586 /* iommus = <&smmu 0x14e8>; */
593 reg = <0x0 0xfd510000 0x0 0x1000>;
599 /* iommus = <&smmu 0x14e9>; */
606 reg = <0x0 0xfd520000 0x0 0x1000>;
612 /* iommus = <&smmu 0x14ea>; */
619 reg = <0x0 0xfd530000 0x0 0x1000>;
625 /* iommus = <&smmu 0x14eb>; */
632 reg = <0x0 0xfd540000 0x0 0x1000>;
638 /* iommus = <&smmu 0x14ec>; */
645 reg = <0x0 0xfd550000 0x0 0x1000>;
651 /* iommus = <&smmu 0x14ed>; */
658 reg = <0x0 0xfd560000 0x0 0x1000>;
664 /* iommus = <&smmu 0x14ee>; */
671 reg = <0x0 0xfd570000 0x0 0x1000>;
677 /* iommus = <&smmu 0x14ef>; */
684 reg = <0x0 0xf9010000 0x0 0x10000>,
685 <0x0 0xf9020000 0x0 0x20000>,
686 <0x0 0xf9040000 0x0 0x20000>,
687 <0x0 0xf9060000 0x0 0x20000>;
696 reg = <0x0 0xfd4b0000 0x0 0x10000>;
716 reg = <0x0 0xffa80000 0x0 0x1000>;
722 /* iommus = <&smmu 0x868>; */
729 reg = <0x0 0xffa90000 0x0 0x1000>;
735 /* iommus = <&smmu 0x869>; */
742 reg = <0x0 0xffaa0000 0x0 0x1000>;
748 /* iommus = <&smmu 0x86a>; */
755 reg = <0x0 0xffab0000 0x0 0x1000>;
761 /* iommus = <&smmu 0x86b>; */
768 reg = <0x0 0xffac0000 0x0 0x1000>;
774 /* iommus = <&smmu 0x86c>; */
781 reg = <0x0 0xffad0000 0x0 0x1000>;
787 /* iommus = <&smmu 0x86d>; */
794 reg = <0x0 0xffae0000 0x0 0x1000>;
800 /* iommus = <&smmu 0x86e>; */
807 reg = <0x0 0xffaf0000 0x0 0x1000>;
813 /* iommus = <&smmu 0x86f>; */
819 reg = <0x0 0xfd070000 0x0 0x30000>;
827 reg = <0x0 0xff100000 0x0 0x1000>;
832 #size-cells = <0>;
833 /* iommus = <&smmu 0x872>; */
843 reg = <0x0 0xff0b0000 0x0 0x1000>;
845 /* iommus = <&smmu 0x874>; */
857 reg = <0x0 0xff0c0000 0x0 0x1000>;
859 /* iommus = <&smmu 0x875>; */
871 reg = <0x0 0xff0d0000 0x0 0x1000>;
873 /* iommus = <&smmu 0x876>; */
885 reg = <0x0 0xff0e0000 0x0 0x1000>;
887 /* iommus = <&smmu 0x877>; */
896 #gpio-cells = <0x2>;
902 reg = <0x0 0xff0a0000 0x0 0x1000>;
912 reg = <0x0 0xff020000 0x0 0x1000>;
914 #size-cells = <0>;
924 reg = <0x0 0xff030000 0x0 0x1000>;
926 #size-cells = <0>;
932 reg = <0x0 0xff960000 0x0 0x1000>;
950 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; /* MSI_0 [31...0] */
954 reg = <0x0 0xfd0e0000 0x0 0x1000>,
955 <0x0 0xfd480000 0x0 0x1000>,
956 <0x80 0x00000000 0x0 0x10000000>;
958 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-pre…
959 …<0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable mem…
960 bus-range = <0x00 0xff>;
961 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
962 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
963 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
964 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
965 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
966 /* iommus = <&smmu 0x4d0>; */
970 #address-cells = <0>;
983 reg = <0x0 0xff0f0000 0x0 0x1000>,
984 <0x0 0xc0000000 0x0 0x8000000>;
986 #size-cells = <0>;
987 /* iommus = <&smmu 0x873>; */
994 reg = <0x0 0xfd400000 0x0 0x40000>,
995 <0x0 0xfd3d0000 0x0 0x1000>;
1003 reg = <0x0 0xffa60000 0x0 0x100>;
1008 calibration = <0x7FFF>;
1014 reg = <0x0 0xfd0c0000 0x0 0x2000>;
1019 /* iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; */
1028 reg = <0x0 0xff160000 0x0 0x1000>;
1030 /* iommus = <&smmu 0x870>; */
1043 reg = <0x0 0xff170000 0x0 0x1000>;
1045 /* iommus = <&smmu 0x871>; */
1054 reg = <0x0 0xfd800000 0x0 0x20000>;
1083 reg = <0x0 0xff040000 0x0 0x1000>;
1086 #size-cells = <0>;
1095 reg = <0x0 0xff050000 0x0 0x1000>;
1098 #size-cells = <0>;
1109 reg = <0x0 0xff110000 0x0 0x1000>;
1121 reg = <0x0 0xff120000 0x0 0x1000>;
1133 reg = <0x0 0xff130000 0x0 0x1000>;
1145 reg = <0x0 0xff140000 0x0 0x1000>;
1156 reg = <0x0 0xff000000 0x0 0x1000>;
1168 reg = <0x0 0xff010000 0x0 0x1000>;
1179 reg = <0x0 0xff9d0000 0x0 0x100>;
1192 reg = <0x0 0xfe200000 0x0 0x40000>;
1200 /* iommus = <&smmu 0x860>; */
1201 snps,quirk-frame-length-adjustment = <0x20>;
1212 reg = <0x0 0xff9e0000 0x0 0x100>;
1224 reg = <0x0 0xfe300000 0x0 0x40000>;
1232 /* iommus = <&smmu 0x861>; */
1233 snps,quirk-frame-length-adjustment = <0x20>;
1244 reg = <0x0 0xfd4d0000 0x0 0x1000>;
1254 reg = <0x0 0xff150000 0x0 0x1000>;
1262 reg = <0x0 0xffa50000 0x0 0x800>;
1266 ranges = <0 0 0xffa50800 0x800>;
1268 ams_ps: ams-ps@0 {
1271 reg = <0x0 0x400>;
1277 reg = <0x400 0x400>;
1284 reg = <0x0 0xfd4c0000 0x0 0x1000>;
1289 /* iommus = <&smmu 0xce4>; */
1297 reg = <0x0 0xfd4a0000 0x0 0x1000>,
1298 <0x0 0xfd4aa000 0x0 0x1000>,
1299 <0x0 0xfd4ab000 0x0 0x1000>,
1300 <0x0 0xfd4ac000 0x0 0x1000>;
1304 /* iommus = <&smmu 0xce3>; */
1320 #size-cells = <0>;
1322 port@0 {
1323 reg = <0>;