Lines Matching +full:0 +full:x2b000000
19 reg = <0x00 0x44083000 0x00 0x1000>;
44 ranges = <0x0 0x00 0x43000000 0x20000>;
49 reg = <0x14 0x4>;
57 reg = <0x00 0x43600000 0x00 0x10000>,
58 <0x00 0x44880000 0x00 0x20000>,
59 <0x00 0x44860000 0x00 0x20000>;
72 reg = <0x00 0x41c00000 0x00 0x100000>;
73 ranges = <0x00 0x00 0x41c00000 0x100000>;
80 /* Proxy 0 addressing */
81 reg = <0x00 0x4301c000 0x00 0x034>;
84 pinctrl-single,function-mask = <0xffffffff>;
89 /* Proxy 0 addressing */
90 reg = <0x00 0x4301c038 0x00 0x02c>;
93 pinctrl-single,function-mask = <0xffffffff>;
98 /* Proxy 0 addressing */
99 reg = <0x00 0x4301c068 0x00 0x120>;
102 pinctrl-single,function-mask = <0xffffffff>;
107 /* Proxy 0 addressing */
108 reg = <0x00 0x4301c190 0x00 0x004>;
111 pinctrl-single,function-mask = <0xffffffff>;
116 reg = <0x00 0x42200000 0x00 0x400>;
129 reg = <0x00 0x40f04200 0x00 0x28>;
132 pinctrl-single,function-mask = <0x0000000f>;
140 reg = <0x00 0x40f04280 0x00 0x28>;
143 pinctrl-single,function-mask = <0x0000000f>;
152 ranges = <0x0 0x0 0x40f00000 0x20000>;
156 reg = <0x200 0x8>;
161 reg = <0x4040 0x4>;
168 reg = <0x00 0x40400000 0x00 0x400>;
183 reg = <0x00 0x40410000 0x00 0x400>;
197 reg = <0x00 0x40420000 0x00 0x400>;
211 reg = <0x00 0x40430000 0x00 0x400>;
225 reg = <0x00 0x40440000 0x00 0x400>;
239 reg = <0x00 0x40450000 0x00 0x400>;
253 reg = <0x00 0x40460000 0x00 0x400>;
267 reg = <0x00 0x40470000 0x00 0x400>;
281 reg = <0x00 0x40480000 0x00 0x400>;
295 reg = <0x00 0x40490000 0x00 0x400>;
309 reg = <0x00 0x42300000 0x00 0x200>;
311 clocks = <&k3_clks 397 0>;
319 reg = <0x00 0x40a00000 0x00 0x200>;
321 clocks = <&k3_clks 149 0>;
329 reg = <0x00 0x42110000 0x00 0x100>;
337 ti,davinci-gpio-unbanked = <0>;
339 clocks = <&k3_clks 167 0>;
346 reg = <0x00 0x42100000 0x00 0x100>;
354 ti,davinci-gpio-unbanked = <0>;
356 clocks = <&k3_clks 168 0>;
363 reg = <0x00 0x42120000 0x00 0x100>;
366 #size-cells = <0>;
375 reg = <0x00 0x40b00000 0x00 0x100>;
378 #size-cells = <0>;
387 reg = <0x00 0x40b10000 0x00 0x100>;
390 #size-cells = <0>;
399 reg = <0x00 0x40528000 0x00 0x200>,
400 <0x00 0x40500000 0x00 0x8000>;
408 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
414 reg = <0x00 0x40568000 0x00 0x200>,
415 <0x00 0x40540000 0x00 0x8000>;
423 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
429 reg = <0x00 0x040300000 0x00 0x400>;
432 #size-cells = <0>;
434 clocks = <&k3_clks 384 0>;
440 reg = <0x00 0x040310000 0x00 0x400>;
443 #size-cells = <0>;
445 clocks = <&k3_clks 385 0>;
451 reg = <0x00 0x040320000 0x00 0x400>;
454 #size-cells = <0>;
456 clocks = <&k3_clks 386 0>;
464 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
472 reg = <0x00 0x2b800000 0x00 0x400000>,
473 <0x00 0x2b000000 0x00 0x400000>,
474 <0x00 0x28590000 0x00 0x100>,
475 <0x00 0x2a500000 0x00 0x40000>,
476 <0x00 0x28440000 0x00 0x40000>;
479 ti,sci-rm-range-gp-rings = <0x1>;
488 reg = <0x00 0x285c0000 0x00 0x100>,
489 <0x00 0x2a800000 0x00 0x40000>,
490 <0x00 0x2aa00000 0x00 0x40000>,
491 <0x00 0x284a0000 0x00 0x4000>,
492 <0x00 0x284c0000 0x00 0x4000>,
493 <0x00 0x28400000 0x00 0x2000>;
502 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
503 <0x0f>; /* TX_HCHAN */
504 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
505 <0x0b>; /* RX_HCHAN */
506 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
514 reg = <0x00 0x2a480000 0x00 0x80000>,
515 <0x00 0x2a380000 0x00 0x80000>,
516 <0x00 0x2a400000 0x00 0x80000>;
531 reg = <0x00 0x46000000 0x00 0x200000>;
533 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
535 clocks = <&k3_clks 63 0>;
539 dmas = <&mcu_udmap 0xf000>,
540 <&mcu_udmap 0xf001>,
541 <&mcu_udmap 0xf002>,
542 <&mcu_udmap 0xf003>,
543 <&mcu_udmap 0xf004>,
544 <&mcu_udmap 0xf005>,
545 <&mcu_udmap 0xf006>,
546 <&mcu_udmap 0xf007>,
547 <&mcu_udmap 0x7000>;
555 #size-cells = <0>;
561 ti,syscon-efuse = <&cpsw_mac_syscon 0x0>;
568 reg = <0x00 0xf00 0x00 0x100>;
570 #size-cells = <0>;
571 clocks = <&k3_clks 63 0>;
578 reg = <0x00 0x3d000 0x00 0x400>;
595 ranges = <0x41000000 0x00 0x41000000 0x20000>,
596 <0x41400000 0x00 0x41400000 0x20000>;
601 reg = <0x41000000 0x00010000>,
602 <0x41010000 0x00010000>;
606 ti,sci-proc-ids = <0x01 0xff>;
616 reg = <0x41400000 0x00010000>,
617 <0x41410000 0x00010000>;
621 ti,sci-proc-ids = <0x02 0xff>;
632 reg = <0x00 0x42040000 0x00 0x350>,
633 <0x00 0x42050000 0x00 0x350>;
641 reg = <0x00 0x40200000 0x00 0x1000>;
643 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
644 clocks = <&k3_clks 0 0>;
645 assigned-clocks = <&k3_clks 0 2>;
648 dmas = <&main_udmap 0x7400>,
649 <&main_udmap 0x7401>;
661 reg = <0x00 0x40210000 0x00 0x1000>;
664 clocks = <&k3_clks 1 0>;
668 dmas = <&main_udmap 0x7402>,
669 <&main_udmap 0x7403>;
683 ranges = <0x00 0x47000000 0x00 0x47000000 0x00 0x00000100>, /* FSS Control */
684 <0x00 0x47040000 0x00 0x47040000 0x00 0x00000100>, /* OSPI0 Control */
685 <0x00 0x47050000 0x00 0x47050000 0x00 0x00000100>, /* OSPI1 Control */
686 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS data region 1 */
687 <0x04 0x00000000 0x04 0x00000000 0x04 0x00000000>; /* FSS data region 0/3 */
691 reg = <0x00 0x47040000 0x00 0x100>,
692 <0x05 0x00000000 0x01 0x00000000>;
696 cdns,trigger-address = <0x0>;
703 #size-cells = <0>;
709 reg = <0x00 0x47050000 0x00 0x100>,
710 <0x07 0x00000000 0x01 0x00000000>;
714 cdns,trigger-address = <0x0>;
718 #size-cells = <0>;
725 reg = <0x00 0x40800000 0x00 0x1000>;
732 reg = <0x00 0x42080000 0x00 0x1000>;
743 reg = <0x00 0x40600000 0x00 0x100>;
746 assigned-clocks = <&k3_clks 367 0>;
754 reg = <0x00 0x40610000 0x00 0x100>;
757 assigned-clocks = <&k3_clks 368 0>;