Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
7 * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
10 #include "k3-j784s4-j742s2-common.dtsi"
17 #address-cells = <1>;
18 #size-cells = <0>;
20 cpu-map {
41 compatible = "arm,cortex-a72";
44 enable-method = "psci";
45 i-cache-size = <0xc000>;
46 i-cache-line-size = <64>;
47 i-cache-sets = <256>;
48 d-cache-size = <0x8000>;
49 d-cache-line-size = <64>;
50 d-cache-sets = <256>;
51 next-level-cache = <&L2_0>;
55 compatible = "arm,cortex-a72";
58 enable-method = "psci";
59 i-cache-size = <0xc000>;
60 i-cache-line-size = <64>;
61 i-cache-sets = <256>;
62 d-cache-size = <0x8000>;
63 d-cache-line-size = <64>;
64 d-cache-sets = <256>;
65 next-level-cache = <&L2_0>;
69 compatible = "arm,cortex-a72";
72 enable-method = "psci";
73 i-cache-size = <0xc000>;
74 i-cache-line-size = <64>;
75 i-cache-sets = <256>;
76 d-cache-size = <0x8000>;
77 d-cache-line-size = <64>;
78 d-cache-sets = <256>;
79 next-level-cache = <&L2_0>;
83 compatible = "arm,cortex-a72";
86 enable-method = "psci";
87 i-cache-size = <0xc000>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <256>;
90 d-cache-size = <0x8000>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <256>;
93 next-level-cache = <&L2_0>;
98 #include "k3-j742s2-main.dtsi"