Lines Matching +full:max +full:- +full:bitrate
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2021-2024 Texas Instruments Incorporated - https://www.ti.com/
8 /dts-v1/;
10 #include "k3-j721s2-som-p0.dtsi"
11 #include <dt-bindings/net/ti-dp83867.h>
12 #include <dt-bindings/phy/phy-cadence.h>
13 #include <dt-bindings/phy/phy.h>
15 #include "k3-serdes.h"
18 compatible = "ti,j721s2-evm", "ti,j721s2";
22 stdout-path = "serial2:115200n8";
37 evm_12v0: fixedregulator-evm12v0 {
39 compatible = "regulator-fixed";
40 regulator-name = "evm_12v0";
41 regulator-min-microvolt = <12000000>;
42 regulator-max-microvolt = <12000000>;
43 regulator-always-on;
44 regulator-boot-on;
47 vsys_3v3: fixedregulator-vsys3v3 {
49 compatible = "regulator-fixed";
50 regulator-name = "vsys_3v3";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 vin-supply = <&evm_12v0>;
54 regulator-always-on;
55 regulator-boot-on;
58 vsys_5v0: fixedregulator-vsys5v0 {
60 compatible = "regulator-fixed";
61 regulator-name = "vsys_5v0";
62 regulator-min-microvolt = <5000000>;
63 regulator-max-microvolt = <5000000>;
64 vin-supply = <&evm_12v0>;
65 regulator-always-on;
66 regulator-boot-on;
69 vdd_mmc1: fixedregulator-sd {
71 compatible = "regulator-fixed";
72 regulator-name = "vdd_mmc1";
73 regulator-min-microvolt = <3300000>;
74 regulator-max-microvolt = <3300000>;
75 regulator-boot-on;
76 enable-active-high;
77 vin-supply = <&vsys_3v3>;
81 vdd_sd_dv: gpio-regulator-TLV71033 {
83 compatible = "regulator-gpio";
84 regulator-name = "tlv71033";
85 pinctrl-names = "default";
86 pinctrl-0 = <&vdd_sd_dv_pins_default>;
87 regulator-min-microvolt = <1800000>;
88 regulator-max-microvolt = <3300000>;
89 regulator-boot-on;
90 vin-supply = <&vsys_5v0>;
96 transceiver1: can-phy1 {
98 #phy-cells = <0>;
99 max-bitrate = <5000000>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
102 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_LOW>;
103 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
106 transceiver2: can-phy2 {
108 #phy-cells = <0>;
109 max-bitrate = <5000000>;
110 pinctrl-names = "default";
111 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
112 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
115 transceiver3: can-phy3 {
117 #phy-cells = <0>;
118 max-bitrate = <5000000>;
119 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
120 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
121 mux-states = <&mux0 1>;
124 transceiver4: can-phy4 {
126 #phy-cells = <0>;
127 max-bitrate = <5000000>;
128 standby-gpios = <&exp_som 7 GPIO_ACTIVE_HIGH>;
129 mux-states = <&mux1 1>;
134 main_uart8_pins_default: main-uart8-default-pins {
135 pinctrl-single,pins = <
141 bootph-all;
144 main_i2c3_pins_default: main-i2c3-default-pins {
145 pinctrl-single,pins = <
151 main_i2c5_pins_default: main-i2c5-default-pins {
152 pinctrl-single,pins = <
158 main_mmc1_pins_default: main-mmc1-default-pins {
159 pinctrl-single,pins = <
169 bootph-all;
172 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
173 pinctrl-single,pins = <
178 main_usbss0_pins_default: main-usbss0-default-pins {
179 pinctrl-single,pins = <
182 bootph-all;
185 main_mcan3_pins_default: main-mcan3-default-pins {
186 pinctrl-single,pins = <
192 main_mcan5_pins_default: main-mcan5-default-pins {
193 pinctrl-single,pins = <
201 wkup_uart0_pins_default: wkup-uart0-default-pins {
202 pinctrl-single,pins = <
206 bootph-all;
209 mcu_uart0_pins_default: mcu-uart0-default-pins {
210 pinctrl-single,pins = <
216 bootph-all;
219 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
220 pinctrl-single,pins = <
236 mcu_mdio_pins_default: mcu-mdio-default-pins {
237 pinctrl-single,pins = <
243 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
244 pinctrl-single,pins = <
250 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
251 pinctrl-single,pins = <
257 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
258 pinctrl-single,pins = <
264 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
265 pinctrl-single,pins = <
270 mcu_adc0_pins_default: mcu-adc0-default-pins {
271 pinctrl-single,pins = <
283 mcu_adc1_pins_default: mcu-adc1-default-pins {
284 pinctrl-single,pins = <
298 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
299 pinctrl-single,pins = <
309 bootph-all;
323 pinctrl-names = "default";
324 pinctrl-0 = <&wkup_uart0_pins_default>;
325 bootph-all;
330 pinctrl-names = "default";
331 pinctrl-0 = <&mcu_uart0_pins_default>;
332 bootph-all;
337 pinctrl-names = "default";
338 pinctrl-0 = <&main_uart8_pins_default>;
340 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>;
341 bootph-all;
345 clock-frequency = <400000>;
350 gpio-controller;
351 #gpio-cells = <2>;
352 gpio-line-names = "PCIE_2L_MODE_SEL", "PCIE_2L_PERSTZ", "PCIE_2L_RC_RSTZ",
362 gpio-controller;
363 #gpio-cells = <2>;
364 gpio-line-names = "APPLE_AUTH_RSTZ", "MLB_RSTZ", "GPIO_USD_PWR_EN", "USBC_PWR_EN",
374 pinctrl-names = "default";
375 pinctrl-0 = <&main_i2c5_pins_default>;
376 clock-frequency = <400000>;
382 gpio-controller;
383 #gpio-cells = <2>;
384 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0",
394 non-removable;
395 bootph-all;
396 ti,driver-strength-ohm = <50>;
397 disable-wp;
403 pinctrl-0 = <&main_mmc1_pins_default>;
404 pinctrl-names = "default";
405 disable-wp;
406 vmmc-supply = <&vdd_mmc1>;
407 vqmmc-supply = <&vdd_sd_dv>;
408 bootph-all;
412 pinctrl-names = "default";
413 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
417 phy0: ethernet-phy@0 {
419 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
420 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
421 ti,min-output-impedance;
426 phy-mode = "rgmii-rxid";
427 phy-handle = <&phy0>;
431 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>,
436 clock-frequency = <100000000>;
443 cdns,num-lanes = <1>;
444 #phy-cells = <0>;
445 cdns,phy-type = <PHY_TYPE_PCIE>;
451 idle-states = <1>; /* USB0 to SERDES lane 1 */
456 pinctrl-0 = <&main_usbss0_pins_default>;
457 pinctrl-names = "default";
458 bootph-all;
459 ti,vbus-divider;
460 ti,usb2-only;
465 maximum-speed = "high-speed";
466 bootph-all;
471 pinctrl-names = "default";
472 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
475 compatible = "jedec,spi-nor";
477 spi-tx-bus-width = <1>;
478 spi-rx-bus-width = <4>;
479 spi-max-frequency = <40000000>;
480 bootph-all;
481 cdns,tshsl-ns = <60>;
482 cdns,tsd2d-ns = <60>;
483 cdns,tchsh-ns = <60>;
484 cdns,tslch-ns = <60>;
485 cdns,read-delay = <2>;
491 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
493 phy-names = "pcie-phy";
494 num-lanes = <1>;
499 pinctrl-names = "default";
500 pinctrl-0 = <&mcu_mcan0_pins_default>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&mcu_mcan1_pins_default>;
512 pinctrl-0 = <&mcu_adc0_pins_default>;
513 pinctrl-names = "default";
516 ti,adc-channels = <0 1 2 3 4 5 6 7>;
521 pinctrl-0 = <&mcu_adc1_pins_default>;
522 pinctrl-names = "default";
525 ti,adc-channels = <0 1 2 3 4 5 6 7>;
531 pinctrl-names = "default";
532 pinctrl-0 = <&main_mcan3_pins_default>;
538 pinctrl-names = "default";
539 pinctrl-0 = <&main_mcan5_pins_default>;