Lines Matching +full:0 +full:x104c
15 #clock-cells = <0>;
17 clock-frequency = <0>;
21 #clock-cells = <0>;
23 clock-frequency = <0>;
30 reg = <0x0 0x70000000 0x0 0x800000>;
33 ranges = <0x0 0x0 0x70000000 0x800000>;
35 atf-sram@0 {
36 reg = <0x0 0x20000>;
42 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
45 ranges = <0x0 0x0 0x00100000 0x1c000>;
49 reg = <0x4080 0x50>;
51 mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */
52 <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */
53 <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */
54 <0x30 0x3>, <0x34 0x3>, /* SERDES3 lane0/1 select */
55 <0x40 0x3>, <0x44 0x3>, /* SERDES4 lane0/1 select */
56 <0x48 0x3>, <0x4c 0x3>; /* SERDES4 lane2/3 select */
68 reg = <0x4044 0x20>;
74 reg = <0x4000 0x20>;
76 mux-reg-masks = <0x0 0x8000000>, /* USB0 to SERDES0/3 mux */
77 <0x10 0x8000000>; /* USB1 to SERDES1/2 mux */
82 reg = <0x4140 0x18>;
90 reg = <0x00 0x3000000 0x00 0x100>;
92 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>;
100 reg = <0x00 0x3010000 0x00 0x100>;
102 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>;
110 reg = <0x00 0x3020000 0x00 0x100>;
112 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>;
120 reg = <0x00 0x3030000 0x00 0x100>;
122 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>;
130 reg = <0x00 0x3040000 0x00 0x100>;
132 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>;
140 reg = <0x00 0x3050000 0x00 0x100>;
142 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>;
154 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
155 <0x00 0x01900000 0x00 0x100000>, /* GICR */
156 <0x00 0x6f000000 0x00 0x2000>, /* GICC */
157 <0x00 0x6f010000 0x00 0x1000>, /* GICH */
158 <0x00 0x6f020000 0x00 0x2000>; /* GICV */
165 reg = <0x00 0x01820000 0x00 0x10000>;
166 socionext,synquacer-pre-its = <0x1000000 0x400000>;
174 reg = <0x00 0x00a00000 0x00 0x800>;
188 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
196 reg = <0x0 0x310e0000 0x0 0x4000>;
203 ti,interrupt-ranges = <0 64 64>,
210 reg = <0x0 0x33d00000 0x0 0x100000>;
214 #interrupt-cells = <0>;
217 ti,interrupt-ranges = <0 0 256>;
224 reg = <0x00 0x32c00000 0x00 0x100000>,
225 <0x00 0x32400000 0x00 0x100000>,
226 <0x00 0x32800000 0x00 0x100000>;
234 reg = <0x0 0x36600000 0x0 0x100000>;
244 reg = <0x00 0x30e00000 0x00 0x1000>;
250 reg = <0x00 0x31f80000 0x00 0x200>;
260 reg = <0x00 0x31f81000 0x00 0x200>;
270 reg = <0x00 0x31f82000 0x00 0x200>;
280 reg = <0x00 0x31f83000 0x00 0x200>;
290 reg = <0x00 0x31f84000 0x00 0x200>;
300 reg = <0x00 0x31f85000 0x00 0x200>;
310 reg = <0x00 0x31f86000 0x00 0x200>;
320 reg = <0x00 0x31f87000 0x00 0x200>;
330 reg = <0x00 0x31f88000 0x00 0x200>;
340 reg = <0x00 0x31f89000 0x00 0x200>;
350 reg = <0x00 0x31f8a000 0x00 0x200>;
360 reg = <0x00 0x31f8b000 0x00 0x200>;
370 reg = <0x0 0x3c000000 0x0 0x400000>,
371 <0x0 0x38000000 0x0 0x400000>,
372 <0x0 0x31120000 0x0 0x100>,
373 <0x0 0x33000000 0x0 0x40000>,
374 <0x0 0x31080000 0x0 0x40000>;
377 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
385 reg = <0x0 0x31150000 0x0 0x100>,
386 <0x0 0x34000000 0x0 0x100000>,
387 <0x0 0x35000000 0x0 0x100000>,
388 <0x0 0x30b00000 0x0 0x20000>,
389 <0x0 0x30c00000 0x0 0x10000>,
390 <0x0 0x30d00000 0x0 0x8000>;
400 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
401 <0x0f>, /* TX_HCHAN */
402 <0x10>; /* TX_UHCHAN */
403 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
404 <0x0b>, /* RX_HCHAN */
405 <0x0c>; /* RX_UHCHAN */
406 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
411 reg = <0x0 0x310d0000 0x0 0x400>;
426 reg = <0x0 0xc000000 0x0 0x200000>;
428 ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
433 dmas = <&main_udmap 0xca00>,
434 <&main_udmap 0xca01>,
435 <&main_udmap 0xca02>,
436 <&main_udmap 0xca03>,
437 <&main_udmap 0xca04>,
438 <&main_udmap 0xca05>,
439 <&main_udmap 0xca06>,
440 <&main_udmap 0xca07>,
441 <&main_udmap 0x4a00>;
450 #size-cells = <0>;
510 reg = <0x0 0xf00 0x0 0x100>;
512 #size-cells = <0>;
521 reg = <0x0 0x3d000 0x0 0x400>;
533 reg = <0x0 0x4e00000 0x0 0x1200>;
537 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
539 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
540 <&main_udmap 0x4001>;
545 reg = <0x0 0x4e10000 0x0 0x7d>;
552 /* Proxy 0 addressing */
553 reg = <0x0 0x11c000 0x0 0x2b4>;
556 pinctrl-single,function-mask = <0xffffffff>;
562 reg = <0x00 0x104200 0x00 0x50>;
565 pinctrl-single,function-mask = <0x00000007>;
571 reg = <0x00 0x104280 0x00 0x20>;
574 pinctrl-single,function-mask = <0x0000001f>;
579 reg = <0x0 0x4500000 0x0 0x1000>;
583 dmas = <&main_udmap 0x4940>;
590 reg = <0x0 0x4504000 0x0 0x1000>;
591 clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>,
600 #size-cells = <0>;
602 csi0_port0: port@0 {
603 reg = <0>;
632 reg = <0x0 0x4510000 0x0 0x1000>;
636 dmas = <&main_udmap 0x4960>;
643 reg = <0x0 0x4514000 0x0 0x1000>;
644 clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>,
653 #size-cells = <0>;
655 csi1_port0: port@0 {
656 reg = <0>;
685 reg = <0x0 0x4580000 0x0 0x1100>;
686 #phy-cells = <0>;
693 reg = <0x0 0x4590000 0x0 0x1100>;
694 #phy-cells = <0>;
706 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
710 ranges = <0x5000000 0x0 0x5000000 0x10000>;
714 #clock-cells = <0>;
720 clocks = <&k3_clks 292 0>, <&cmn_refclk1>;
721 #clock-cells = <0>;
723 assigned-clock-parents = <&k3_clks 292 0>;
727 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&cmn_refclk>, <&cmn_refclk1>;
728 #clock-cells = <0>;
735 #clock-cells = <0>;
740 #clock-cells = <0>;
746 reg = <0x5000000 0x10000>;
748 #size-cells = <0>;
750 resets = <&serdes_wiz0 0>;
766 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
770 ranges = <0x5010000 0x0 0x5010000 0x10000>;
774 #clock-cells = <0>;
780 clocks = <&k3_clks 293 0>, <&cmn_refclk1>;
781 #clock-cells = <0>;
783 assigned-clock-parents = <&k3_clks 293 0>;
787 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&cmn_refclk>, <&cmn_refclk1>;
788 #clock-cells = <0>;
795 #clock-cells = <0>;
800 #clock-cells = <0>;
806 reg = <0x5010000 0x10000>;
808 #size-cells = <0>;
810 resets = <&serdes_wiz1 0>;
826 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
830 ranges = <0x5020000 0x0 0x5020000 0x10000>;
834 #clock-cells = <0>;
840 clocks = <&k3_clks 294 0>, <&cmn_refclk1>;
841 #clock-cells = <0>;
843 assigned-clock-parents = <&k3_clks 294 0>;
847 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&cmn_refclk>, <&cmn_refclk1>;
848 #clock-cells = <0>;
855 #clock-cells = <0>;
860 #clock-cells = <0>;
866 reg = <0x5020000 0x10000>;
868 #size-cells = <0>;
870 resets = <&serdes_wiz2 0>;
886 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
890 ranges = <0x5030000 0x0 0x5030000 0x10000>;
894 #clock-cells = <0>;
900 clocks = <&k3_clks 295 0>, <&cmn_refclk1>;
901 #clock-cells = <0>;
903 assigned-clock-parents = <&k3_clks 295 0>;
907 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&cmn_refclk>, <&cmn_refclk1>;
908 #clock-cells = <0>;
915 #clock-cells = <0>;
920 #clock-cells = <0>;
926 reg = <0x5030000 0x10000>;
928 #size-cells = <0>;
930 resets = <&serdes_wiz3 0>;
941 reg = <0x00 0x02900000 0x00 0x1000>,
942 <0x00 0x02907000 0x00 0x400>,
943 <0x00 0x0d000000 0x00 0x00800000>,
944 <0x00 0x10000000 0x00 0x00001000>;
949 ti,syscon-pcie-ctrl = <&scm_conf 0x4070>;
957 bus-range = <0x0 0xff>;
958 vendor-id = <0x104c>;
959 device-id = <0xb00d>;
960 msi-map = <0x0 &gic_its 0x0 0x10000>;
962 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
963 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
964 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
970 reg = <0x00 0x02910000 0x00 0x1000>,
971 <0x00 0x02917000 0x00 0x400>,
972 <0x00 0x0d800000 0x00 0x00800000>,
973 <0x00 0x18000000 0x00 0x00001000>;
978 ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
986 bus-range = <0x0 0xff>;
987 vendor-id = <0x104c>;
988 device-id = <0xb00d>;
989 msi-map = <0x0 &gic_its 0x10000 0x10000>;
991 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
992 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
993 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
999 reg = <0x00 0x02920000 0x00 0x1000>,
1000 <0x00 0x02927000 0x00 0x400>,
1001 <0x00 0x0e000000 0x00 0x00800000>,
1002 <0x44 0x00000000 0x00 0x00001000>;
1007 ti,syscon-pcie-ctrl = <&scm_conf 0x4078>;
1015 bus-range = <0x0 0xff>;
1016 vendor-id = <0x104c>;
1017 device-id = <0xb00d>;
1018 msi-map = <0x0 &gic_its 0x20000 0x10000>;
1020 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
1021 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
1022 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1028 reg = <0x00 0x02930000 0x00 0x1000>,
1029 <0x00 0x02937000 0x00 0x400>,
1030 <0x00 0x0e800000 0x00 0x00800000>,
1031 <0x44 0x10000000 0x00 0x00001000>;
1036 ti,syscon-pcie-ctrl = <&scm_conf 0x407c>;
1044 bus-range = <0x0 0xff>;
1045 vendor-id = <0x104c>;
1046 device-id = <0xb00d>;
1047 msi-map = <0x0 &gic_its 0x30000 0x10000>;
1049 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
1050 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
1051 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
1068 ranges = <0x05050000 0x00 0x05050000 0x010000>,
1069 <0x0a030a00 0x00 0x0a030a00 0x40>;
1077 reg = <0x05050000 0x010000>,
1078 <0x0a030a00 0x40>; /* DPTX PHY */
1081 resets = <&serdes_wiz4 0>;
1092 #size-cells = <0>;
1098 reg = <0x00 0x2400000 0x00 0x400>;
1110 reg = <0x00 0x2410000 0x00 0x400>;
1114 assigned-clocks = <&k3_clks 50 1>, <&k3_clks 327 0>;
1122 reg = <0x00 0x2420000 0x00 0x400>;
1134 reg = <0x00 0x2430000 0x00 0x400>;
1138 assigned-clocks = <&k3_clks 52 1>, <&k3_clks 328 0>;
1146 reg = <0x00 0x2440000 0x00 0x400>;
1158 reg = <0x00 0x2450000 0x00 0x400>;
1162 assigned-clocks = <&k3_clks 54 1>, <&k3_clks 329 0>;
1170 reg = <0x00 0x2460000 0x00 0x400>;
1182 reg = <0x00 0x2470000 0x00 0x400>;
1186 assigned-clocks = <&k3_clks 57 1>, <&k3_clks 330 0>;
1194 reg = <0x00 0x2480000 0x00 0x400>;
1206 reg = <0x00 0x2490000 0x00 0x400>;
1210 assigned-clocks = <&k3_clks 59 1>, <&k3_clks 331 0>;
1218 reg = <0x00 0x24a0000 0x00 0x400>;
1230 reg = <0x00 0x24b0000 0x00 0x400>;
1234 assigned-clocks = <&k3_clks 62 1>, <&k3_clks 332 0>;
1242 reg = <0x00 0x24c0000 0x00 0x400>;
1254 reg = <0x00 0x24d0000 0x00 0x400>;
1258 assigned-clocks = <&k3_clks 64 1>, <&k3_clks 333 0>;
1266 reg = <0x00 0x24e0000 0x00 0x400>;
1278 reg = <0x00 0x24f0000 0x00 0x400>;
1282 assigned-clocks = <&k3_clks 66 1>, <&k3_clks 334 0>;
1290 reg = <0x00 0x2500000 0x00 0x400>;
1302 reg = <0x00 0x2510000 0x00 0x400>;
1306 assigned-clocks = <&k3_clks 68 1>, <&k3_clks 335 0>;
1314 reg = <0x00 0x2520000 0x00 0x400>;
1326 reg = <0x00 0x2530000 0x00 0x400>;
1330 assigned-clocks = <&k3_clks 70 1>, <&k3_clks 336 0>;
1338 reg = <0x00 0x02800000 0x00 0x100>;
1342 clocks = <&k3_clks 146 0>;
1349 reg = <0x00 0x02810000 0x00 0x100>;
1353 clocks = <&k3_clks 278 0>;
1360 reg = <0x00 0x02820000 0x00 0x100>;
1364 clocks = <&k3_clks 279 0>;
1371 reg = <0x00 0x02830000 0x00 0x100>;
1375 clocks = <&k3_clks 280 0>;
1382 reg = <0x00 0x02840000 0x00 0x100>;
1386 clocks = <&k3_clks 281 0>;
1393 reg = <0x00 0x02850000 0x00 0x100>;
1397 clocks = <&k3_clks 282 0>;
1404 reg = <0x00 0x02860000 0x00 0x100>;
1408 clocks = <&k3_clks 283 0>;
1415 reg = <0x00 0x02870000 0x00 0x100>;
1419 clocks = <&k3_clks 284 0>;
1426 reg = <0x00 0x02880000 0x00 0x100>;
1430 clocks = <&k3_clks 285 0>;
1437 reg = <0x00 0x02890000 0x00 0x100>;
1441 clocks = <&k3_clks 286 0>;
1448 reg = <0x0 0x00600000 0x0 0x100>;
1457 ti,davinci-gpio-unbanked = <0>;
1459 clocks = <&k3_clks 105 0>;
1466 reg = <0x0 0x00601000 0x0 0x100>;
1474 ti,davinci-gpio-unbanked = <0>;
1476 clocks = <&k3_clks 106 0>;
1483 reg = <0x0 0x00610000 0x0 0x100>;
1492 ti,davinci-gpio-unbanked = <0>;
1494 clocks = <&k3_clks 107 0>;
1501 reg = <0x0 0x00611000 0x0 0x100>;
1509 ti,davinci-gpio-unbanked = <0>;
1511 clocks = <&k3_clks 108 0>;
1518 reg = <0x0 0x00620000 0x0 0x100>;
1527 ti,davinci-gpio-unbanked = <0>;
1529 clocks = <&k3_clks 109 0>;
1536 reg = <0x0 0x00621000 0x0 0x100>;
1544 ti,davinci-gpio-unbanked = <0>;
1546 clocks = <&k3_clks 110 0>;
1553 reg = <0x0 0x00630000 0x0 0x100>;
1562 ti,davinci-gpio-unbanked = <0>;
1564 clocks = <&k3_clks 111 0>;
1571 reg = <0x0 0x00631000 0x0 0x100>;
1579 ti,davinci-gpio-unbanked = <0>;
1581 clocks = <&k3_clks 112 0>;
1588 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1592 clocks = <&k3_clks 91 0>, <&k3_clks 91 1>;
1598 ti,otap-del-sel-legacy = <0x0>;
1599 ti,otap-del-sel-mmc-hs = <0x0>;
1600 ti,otap-del-sel-ddr52 = <0x5>;
1601 ti,otap-del-sel-hs200 = <0x6>;
1602 ti,otap-del-sel-hs400 = <0x0>;
1603 ti,itap-del-sel-legacy = <0x10>;
1604 ti,itap-del-sel-mmc-hs = <0xa>;
1605 ti,itap-del-sel-ddr52 = <0x3>;
1606 ti,trm-icp = <0x8>;
1613 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1617 clocks = <&k3_clks 92 5>, <&k3_clks 92 0>;
1618 assigned-clocks = <&k3_clks 92 0>;
1620 ti,otap-del-sel-legacy = <0x0>;
1621 ti,otap-del-sel-sd-hs = <0x0>;
1622 ti,otap-del-sel-sdr12 = <0xf>;
1623 ti,otap-del-sel-sdr25 = <0xf>;
1624 ti,otap-del-sel-sdr50 = <0xc>;
1625 ti,otap-del-sel-ddr50 = <0xc>;
1626 ti,otap-del-sel-sdr104 = <0x5>;
1627 ti,itap-del-sel-legacy = <0x0>;
1628 ti,itap-del-sel-sd-hs = <0x0>;
1629 ti,itap-del-sel-sdr12 = <0x0>;
1630 ti,itap-del-sel-sdr25 = <0x0>;
1631 ti,itap-del-sel-ddr50 = <0x2>;
1632 ti,trm-icp = <0x8>;
1633 ti,clkbuf-sel = <0x7>;
1635 sdhci-caps-mask = <0x2 0x0>;
1641 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1645 clocks = <&k3_clks 93 5>, <&k3_clks 93 0>;
1646 assigned-clocks = <&k3_clks 93 0>;
1648 ti,otap-del-sel-legacy = <0x0>;
1649 ti,otap-del-sel-sd-hs = <0x0>;
1650 ti,otap-del-sel-sdr12 = <0xf>;
1651 ti,otap-del-sel-sdr25 = <0xf>;
1652 ti,otap-del-sel-sdr50 = <0xc>;
1653 ti,otap-del-sel-ddr50 = <0xc>;
1654 ti,otap-del-sel-sdr104 = <0x5>;
1655 ti,itap-del-sel-legacy = <0x0>;
1656 ti,itap-del-sel-sd-hs = <0x0>;
1657 ti,itap-del-sel-sdr12 = <0x0>;
1658 ti,itap-del-sel-sdr25 = <0x0>;
1659 ti,itap-del-sel-ddr50 = <0x2>;
1660 ti,trm-icp = <0x8>;
1661 ti,clkbuf-sel = <0x7>;
1663 sdhci-caps-mask = <0x2 0x0>;
1669 reg = <0x00 0x4104000 0x00 0x100>;
1682 reg = <0x00 0x6000000 0x00 0x10000>,
1683 <0x00 0x6010000 0x00 0x10000>,
1684 <0x00 0x6020000 0x00 0x10000>;
1686 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1688 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1699 reg = <0x00 0x4114000 0x00 0x100>;
1712 reg = <0x00 0x6400000 0x00 0x10000>,
1713 <0x00 0x6410000 0x00 0x10000>,
1714 <0x00 0x6420000 0x00 0x10000>;
1716 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1718 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1729 reg = <0x0 0x2000000 0x0 0x100>;
1732 #size-cells = <0>;
1734 clocks = <&k3_clks 187 0>;
1741 reg = <0x0 0x2010000 0x0 0x100>;
1744 #size-cells = <0>;
1746 clocks = <&k3_clks 188 0>;
1753 reg = <0x0 0x2020000 0x0 0x100>;
1756 #size-cells = <0>;
1758 clocks = <&k3_clks 189 0>;
1765 reg = <0x0 0x2030000 0x0 0x100>;
1768 #size-cells = <0>;
1770 clocks = <&k3_clks 190 0>;
1777 reg = <0x0 0x2040000 0x0 0x100>;
1780 #size-cells = <0>;
1782 clocks = <&k3_clks 191 0>;
1789 reg = <0x0 0x2050000 0x0 0x100>;
1792 #size-cells = <0>;
1794 clocks = <&k3_clks 192 0>;
1801 reg = <0x0 0x2060000 0x0 0x100>;
1804 #size-cells = <0>;
1806 clocks = <&k3_clks 193 0>;
1813 reg = <0x0 0x4e80000 0x0 0x100>;
1824 reg = <0x0 0x4e84000 0x0 0x10000>;
1827 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1839 reg = <0x00 0x0a000000 0x00 0x030a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
1840 <0x00 0x04f40000 0x00 0x20>; /* DSS_EDP0_INTG_CFG_VP */
1852 #size-cells = <0>;
1854 port@0 {
1855 reg = <0>;
1867 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1868 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1869 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1870 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1872 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1873 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1874 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1875 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1877 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1878 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1879 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1880 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1882 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1883 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1884 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1885 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1886 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1895 clocks = <&k3_clks 152 0>,
1919 reg = <0x0 0x02b00000 0x0 0x2000>,
1920 <0x0 0x02b08000 0x0 0x1000>;
1926 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1937 reg = <0x0 0x02b10000 0x0 0x2000>,
1938 <0x0 0x02b18000 0x0 0x1000>;
1944 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1955 reg = <0x0 0x02b20000 0x0 0x2000>,
1956 <0x0 0x02b28000 0x0 0x1000>;
1962 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1973 reg = <0x0 0x02b30000 0x0 0x2000>,
1974 <0x0 0x02b38000 0x0 0x1000>;
1980 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1991 reg = <0x0 0x02b40000 0x0 0x2000>,
1992 <0x0 0x02b48000 0x0 0x1000>;
1998 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
2009 reg = <0x0 0x02b50000 0x0 0x2000>,
2010 <0x0 0x02b58000 0x0 0x1000>;
2016 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
2027 reg = <0x0 0x02b60000 0x0 0x2000>,
2028 <0x0 0x02b68000 0x0 0x1000>;
2034 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
2045 reg = <0x0 0x02b70000 0x0 0x2000>,
2046 <0x0 0x02b78000 0x0 0x1000>;
2052 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
2063 reg = <0x0 0x02b80000 0x0 0x2000>,
2064 <0x0 0x02b88000 0x0 0x1000>;
2070 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
2081 reg = <0x0 0x02b90000 0x0 0x2000>,
2082 <0x0 0x02b98000 0x0 0x1000>;
2088 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
2099 reg = <0x0 0x02ba0000 0x0 0x2000>,
2100 <0x0 0x02ba8000 0x0 0x1000>;
2106 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
2117 reg = <0x0 0x02bb0000 0x0 0x2000>,
2118 <0x0 0x02bb8000 0x0 0x1000>;
2124 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
2135 reg = <0x0 0x2200000 0x0 0x100>;
2144 reg = <0x0 0x2210000 0x0 0x100>;
2156 ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
2157 <0x5d00000 0x00 0x5d00000 0x20000>;
2162 reg = <0x5c00000 0x00008000>,
2163 <0x5c10000 0x00008000>;
2167 ti,sci-proc-ids = <0x06 0xff>;
2177 reg = <0x5d00000 0x00008000>,
2178 <0x5d10000 0x00008000>;
2182 ti,sci-proc-ids = <0x07 0xff>;
2196 ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
2197 <0x5f00000 0x00 0x5f00000 0x20000>;
2202 reg = <0x5e00000 0x00008000>,
2203 <0x5e10000 0x00008000>;
2207 ti,sci-proc-ids = <0x08 0xff>;
2217 reg = <0x5f00000 0x00008000>,
2218 <0x5f10000 0x00008000>;
2222 ti,sci-proc-ids = <0x09 0xff>;
2233 reg = <0x4d 0x80800000 0x00 0x00048000>,
2234 <0x4d 0x80e00000 0x00 0x00008000>,
2235 <0x4d 0x80f00000 0x00 0x00008000>;
2239 ti,sci-proc-ids = <0x03 0xff>;
2247 reg = <0x4d 0x81800000 0x00 0x00048000>,
2248 <0x4d 0x81e00000 0x00 0x00008000>,
2249 <0x4d 0x81f00000 0x00 0x00008000>;
2253 ti,sci-proc-ids = <0x04 0xff>;
2261 reg = <0x00 0x64800000 0x00 0x00080000>,
2262 <0x00 0x64e00000 0x00 0x0000c000>;
2266 ti,sci-proc-ids = <0x30 0xff>;
2274 reg = <0x00 0xb000000 0x00 0x80000>;
2278 ranges = <0x0 0x00 0x0b000000 0x100000>;
2280 icssg0_mem: memories@0 {
2281 reg = <0x0 0x2000>,
2282 <0x2000 0x2000>,
2283 <0x10000 0x10000>;
2290 reg = <0x26000 0x200>;
2293 ranges = <0x0 0x26000 0x2000>;
2297 #size-cells = <0>;
2300 reg = <0x3c>;
2301 #clock-cells = <0>;
2309 reg = <0x30>;
2310 #clock-cells = <0>;
2321 reg = <0x32000 0x100>;
2326 reg = <0x33000 0x1000>;
2331 reg = <0x20000 0x2000>;
2350 reg = <0x34000 0x3000>,
2351 <0x22000 0x100>,
2352 <0x22400 0x100>;
2359 reg = <0x4000 0x2000>,
2360 <0x23000 0x100>,
2361 <0x23400 0x100>;
2368 reg = <0xa000 0x1800>,
2369 <0x25000 0x100>,
2370 <0x25400 0x100>;
2377 reg = <0x38000 0x3000>,
2378 <0x24000 0x100>,
2379 <0x24400 0x100>;
2386 reg = <0x6000 0x2000>,
2387 <0x23800 0x100>,
2388 <0x23c00 0x100>;
2395 reg = <0xc000 0x1800>,
2396 <0x25800 0x100>,
2397 <0x25c00 0x100>;
2404 reg = <0x32400 0x100>;
2408 #size-cells = <0>;
2416 reg = <0x00 0xb100000 0x00 0x80000>;
2420 ranges = <0x0 0x00 0x0b100000 0x100000>;
2423 reg = <0x0 0x2000>,
2424 <0x2000 0x2000>,
2425 <0x10000 0x10000>;
2432 reg = <0x26000 0x200>;
2435 ranges = <0x0 0x26000 0x2000>;
2439 #size-cells = <0>;
2442 reg = <0x3c>;
2443 #clock-cells = <0>;
2451 reg = <0x30>;
2452 #clock-cells = <0>;
2463 reg = <0x32000 0x100>;
2468 reg = <0x33000 0x1000>;
2473 reg = <0x20000 0x2000>;
2492 reg = <0x34000 0x4000>,
2493 <0x22000 0x100>,
2494 <0x22400 0x100>;
2501 reg = <0x4000 0x2000>,
2502 <0x23000 0x100>,
2503 <0x23400 0x100>;
2510 reg = <0xa000 0x1800>,
2511 <0x25000 0x100>,
2512 <0x25400 0x100>;
2519 reg = <0x38000 0x4000>,
2520 <0x24000 0x100>,
2521 <0x24400 0x100>;
2528 reg = <0x6000 0x2000>,
2529 <0x23800 0x100>,
2530 <0x23c00 0x100>;
2537 reg = <0xc000 0x1800>,
2538 <0x25800 0x100>,
2539 <0x25c00 0x100>;
2546 reg = <0x32400 0x100>;
2550 #size-cells = <0>;
2558 reg = <0x00 0x02701000 0x00 0x200>,
2559 <0x00 0x02708000 0x00 0x8000>;
2562 clocks = <&k3_clks 156 0>, <&k3_clks 156 1>;
2567 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2573 reg = <0x00 0x02711000 0x00 0x200>,
2574 <0x00 0x02718000 0x00 0x8000>;
2577 clocks = <&k3_clks 158 0>, <&k3_clks 158 1>;
2582 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2588 reg = <0x00 0x02721000 0x00 0x200>,
2589 <0x00 0x02728000 0x00 0x8000>;
2592 clocks = <&k3_clks 160 0>, <&k3_clks 160 1>;
2597 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2603 reg = <0x00 0x02731000 0x00 0x200>,
2604 <0x00 0x02738000 0x00 0x8000>;
2607 clocks = <&k3_clks 161 0>, <&k3_clks 161 1>;
2612 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2618 reg = <0x00 0x02741000 0x00 0x200>,
2619 <0x00 0x02748000 0x00 0x8000>;
2622 clocks = <&k3_clks 162 0>, <&k3_clks 162 1>;
2627 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2633 reg = <0x00 0x02751000 0x00 0x200>,
2634 <0x00 0x02758000 0x00 0x8000>;
2637 clocks = <&k3_clks 163 0>, <&k3_clks 163 1>;
2642 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2648 reg = <0x00 0x02761000 0x00 0x200>,
2649 <0x00 0x02768000 0x00 0x8000>;
2652 clocks = <&k3_clks 164 0>, <&k3_clks 164 1>;
2657 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2663 reg = <0x00 0x02771000 0x00 0x200>,
2664 <0x00 0x02778000 0x00 0x8000>;
2667 clocks = <&k3_clks 165 0>, <&k3_clks 165 1>;
2672 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2678 reg = <0x00 0x02781000 0x00 0x200>,
2679 <0x00 0x02788000 0x00 0x8000>;
2682 clocks = <&k3_clks 166 0>, <&k3_clks 166 1>;
2687 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2693 reg = <0x00 0x02791000 0x00 0x200>,
2694 <0x00 0x02798000 0x00 0x8000>;
2697 clocks = <&k3_clks 167 0>, <&k3_clks 167 1>;
2702 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2708 reg = <0x00 0x027a1000 0x00 0x200>,
2709 <0x00 0x027a8000 0x00 0x8000>;
2712 clocks = <&k3_clks 168 0>, <&k3_clks 168 1>;
2717 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2723 reg = <0x00 0x027b1000 0x00 0x200>,
2724 <0x00 0x027b8000 0x00 0x8000>;
2727 clocks = <&k3_clks 169 0>, <&k3_clks 169 1>;
2732 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2738 reg = <0x00 0x027c1000 0x00 0x200>,
2739 <0x00 0x027c8000 0x00 0x8000>;
2742 clocks = <&k3_clks 170 0>, <&k3_clks 170 1>;
2747 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2753 reg = <0x00 0x027d1000 0x00 0x200>,
2754 <0x00 0x027d8000 0x00 0x8000>;
2757 clocks = <&k3_clks 171 0>, <&k3_clks 171 1>;
2762 bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
2768 reg = <0x00 0x02100000 0x00 0x400>;
2771 #size-cells = <0>;
2779 reg = <0x00 0x02110000 0x00 0x400>;
2782 #size-cells = <0>;
2790 reg = <0x00 0x02120000 0x00 0x400>;
2793 #size-cells = <0>;
2801 reg = <0x00 0x02130000 0x00 0x400>;
2804 #size-cells = <0>;
2812 reg = <0x00 0x02140000 0x00 0x400>;
2815 #size-cells = <0>;
2823 reg = <0x00 0x02150000 0x00 0x400>;
2826 #size-cells = <0>;
2834 reg = <0x00 0x02160000 0x00 0x400>;
2837 #size-cells = <0>;
2845 reg = <0x00 0x02170000 0x00 0x400>;
2848 #size-cells = <0>;
2856 reg = <0x0 0x700000 0x0 0x1000>;