Lines Matching +full:max +full:- +full:bitrate
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
3 * Copyright (C) 2020-2024 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j7200-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/net/ti-dp83867.h>
11 #include <dt-bindings/phy/phy.h>
13 #include "k3-serdes.h"
16 compatible = "ti,j7200-evm", "ti,j7200";
30 stdout-path = "serial2:115200n8";
33 evm_12v0: fixedregulator-evm12v0 {
35 compatible = "regulator-fixed";
36 regulator-name = "evm_12v0";
37 regulator-min-microvolt = <12000000>;
38 regulator-max-microvolt = <12000000>;
39 regulator-always-on;
40 regulator-boot-on;
43 vsys_3v3: fixedregulator-vsys3v3 {
45 compatible = "regulator-fixed";
46 regulator-name = "vsys_3v3";
47 regulator-min-microvolt = <3300000>;
48 regulator-max-microvolt = <3300000>;
49 vin-supply = <&evm_12v0>;
50 regulator-always-on;
51 regulator-boot-on;
54 vsys_5v0: fixedregulator-vsys5v0 {
56 compatible = "regulator-fixed";
57 regulator-name = "vsys_5v0";
58 regulator-min-microvolt = <5000000>;
59 regulator-max-microvolt = <5000000>;
60 vin-supply = <&evm_12v0>;
61 regulator-always-on;
62 regulator-boot-on;
65 vdd_mmc1: fixedregulator-sd {
67 compatible = "regulator-fixed";
68 regulator-name = "vdd_mmc1";
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 regulator-boot-on;
72 enable-active-high;
73 vin-supply = <&vsys_3v3>;
77 vdd_sd_dv: gpio-regulator-TLV71033 {
79 compatible = "regulator-gpio";
80 regulator-name = "tlv71033";
81 pinctrl-names = "default";
82 pinctrl-0 = <&vdd_sd_dv_pins_default>;
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <3300000>;
85 regulator-boot-on;
86 vin-supply = <&vsys_5v0>;
92 transceiver1: can-phy1 {
94 #phy-cells = <0>;
95 max-bitrate = <5000000>;
96 pinctrl-names = "default";
97 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
98 standby-gpios = <&wkup_gpio0 58 GPIO_ACTIVE_LOW>;
99 enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
102 transceiver2: can-phy2 {
104 #phy-cells = <0>;
105 max-bitrate = <5000000>;
106 pinctrl-names = "default";
107 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
108 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
111 transceiver3: can-phy3 {
113 #phy-cells = <0>;
114 max-bitrate = <5000000>;
115 standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
116 enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
117 mux-states = <&mux0 1>;
125 mcu_uart0_pins_default: mcu-uart0-default-pins {
126 pinctrl-single,pins = <
132 bootph-all;
135 wkup_uart0_pins_default: wkup-uart0-default-pins {
136 pinctrl-single,pins = <
140 bootph-all;
143 mcu_cpsw_pins_default: mcu-cpsw-default-pins {
144 pinctrl-single,pins = <
160 wkup_gpio_pins_default: wkup-gpio-default-pins {
161 pinctrl-single,pins = <
166 mcu_mdio_pins_default: mcu-mdio1-default-pins {
167 pinctrl-single,pins = <
173 mcu_mcan0_pins_default: mcu-mcan0-default-pins {
174 pinctrl-single,pins = <
180 mcu_mcan1_pins_default: mcu-mcan1-default-pins {
181 pinctrl-single,pins = <
187 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
188 pinctrl-single,pins = <
194 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
195 pinctrl-single,pins = <
202 main_uart0_pins_default: main-uart0-default-pins {
203 pinctrl-single,pins = <
209 bootph-all;
212 main_uart1_pins_default: main-uart1-default-pins {
213 pinctrl-single,pins = <
219 main_uart3_pins_default: main-uart3-default-pins {
220 pinctrl-single,pins = <
226 main_i2c1_pins_default: main-i2c1-default-pins {
227 pinctrl-single,pins = <
233 main_mmc1_pins_default: main-mmc1-default-pins {
234 pinctrl-single,pins = <
244 bootph-all;
247 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins {
248 pinctrl-single,pins = <
253 main_mcan3_pins_default: main-mcan3-default-pins {
254 pinctrl-single,pins = <
262 main_usbss0_pins_default: main-usbss0-default-pins {
263 pinctrl-single,pins = <
266 bootph-all;
273 pinctrl-names = "default";
274 pinctrl-0 = <&wkup_uart0_pins_default>;
275 bootph-all;
280 pinctrl-names = "default";
281 pinctrl-0 = <&mcu_uart0_pins_default>;
282 bootph-all;
288 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
289 pinctrl-names = "default";
290 pinctrl-0 = <&main_uart0_pins_default>;
291 bootph-all;
297 pinctrl-names = "default";
298 pinctrl-0 = <&main_uart1_pins_default>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&main_uart3_pins_default>;
319 pinctrl-names = "default";
320 pinctrl-0 = <&wkup_gpio_pins_default>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;
329 phy0: ethernet-phy@0 {
331 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
332 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
337 phy-mode = "rgmii-rxid";
338 phy-handle = <&phy0>;
343 pinctrl-names = "default";
344 pinctrl-0 = <&main_i2c0_pins_default>;
345 clock-frequency = <400000>;
350 gpio-controller;
351 #gpio-cells = <2>;
357 gpio-controller;
358 #gpio-cells = <2>;
371 pinctrl-names = "default";
372 pinctrl-0 = <&main_i2c1_pins_default>;
373 clock-frequency = <400000>;
378 gpio-controller;
379 #gpio-cells = <2>;
380 gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
389 non-removable;
390 bootph-all;
391 ti,driver-strength-ohm = <50>;
392 disable-wp;
398 pinctrl-0 = <&main_mmc1_pins_default>;
399 pinctrl-names = "default";
400 vmmc-supply = <&vdd_mmc1>;
401 vqmmc-supply = <&vdd_sd_dv>;
402 bootph-all;
403 ti,driver-strength-ohm = <50>;
404 disable-wp;
408 idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
413 mux-controls = <&spi1_linkdis 0>;
417 idle-states = <1>; /* USB0 to SERDES lane 3 */
418 bootph-all;
422 pinctrl-names = "default";
423 pinctrl-0 = <&main_usbss0_pins_default>;
424 bootph-all;
425 ti,vbus-divider;
426 ti,usb2-only;
431 maximum-speed = "high-speed";
432 bootph-all;
437 ti,adc-channels = <0 1 2 3 4 5 6 7>;
442 clock-frequency = <100000000>;
448 cdns,num-lanes = <2>;
449 #phy-cells = <0>;
450 cdns,phy-type = <PHY_TYPE_PCIE>;
456 cdns,num-lanes = <1>;
457 #phy-cells = <0>;
458 cdns,phy-type = <PHY_TYPE_QSGMII>;
465 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
467 phy-names = "pcie-phy";
468 num-lanes = <2>;
473 pinctrl-names = "default";
474 pinctrl-0 = <&mcu_mcan0_pins_default>;
480 pinctrl-names = "default";
481 pinctrl-0 = <&mcu_mcan1_pins_default>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&main_mcan3_pins_default>;