Lines Matching +full:stm32 +full:- +full:exti
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
3 * Copyright (C) STMicroelectronics 2023 - All Rights Reserved
6 #include <dt-bindings/clock/st,stm32mp25-rcc.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/reset/st,stm32mp25-rcc.h>
9 #include <dt-bindings/regulator/st,stm32mp25-regulator.h>
10 #include <dt-bindings/phy/phy.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "arm,cortex-a35";
24 enable-method = "psci";
25 power-domains = <&CPU_PD0>;
26 power-domain-names = "psci";
30 arm-pmu {
31 compatible = "arm,cortex-a35-pmu";
33 interrupt-affinity = <&cpu0>;
34 interrupt-parent = <&intc>;
38 compatible = "arm,smc-wdt";
39 arm,smc-id = <0xb200005a>;
45 #clock-cells = <0>;
46 compatible = "fixed-clock";
47 clock-frequency = <0>;
50 clk_rcbsec: clk-rcbsec {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <64000000>;
59 compatible = "linaro,optee-tz";
61 interrupt-parent = <&intc>;
66 compatible = "linaro,scmi-optee";
67 #address-cells = <1>;
68 #size-cells = <0>;
69 linaro,optee-channel-id = <0>;
73 #clock-cells = <1>;
78 #reset-cells = <1>;
85 #address-cells = <1>;
86 #size-cells = <0>;
90 regulator-name = "vddio1";
94 regulator-name = "vddio2";
98 regulator-name = "vddio3";
102 regulator-name = "vddio4";
106 regulator-name = "vdd33ucpd";
110 regulator-name = "vdda18adc";
117 intc: interrupt-controller@4ac00000 {
118 compatible = "arm,cortex-a7-gic";
119 #interrupt-cells = <3>;
120 #address-cells = <1>;
121 interrupt-controller;
129 compatible = "arm,psci-1.0";
132 CPU_PD0: power-domain-cpu0 {
133 #power-domain-cells = <0>;
134 power-domains = <&CLUSTER_PD>;
137 CLUSTER_PD: power-domain-cluster {
138 #power-domain-cells = <0>;
139 power-domains = <&RET_PD>;
142 RET_PD: power-domain-retention {
143 #power-domain-cells = <0>;
148 compatible = "arm,armv8-timer";
149 interrupt-parent = <&intc>;
154 always-on;
158 compatible = "simple-bus";
159 #address-cells = <1>;
160 #size-cells = <1>;
161 interrupt-parent = <&intc>;
164 hpdma: dma-controller@40400000 {
165 compatible = "st,stm32mp25-dma3";
184 #dma-cells = <3>;
187 hpdma2: dma-controller@40410000 {
188 compatible = "st,stm32mp25-dma3";
207 #dma-cells = <3>;
210 hpdma3: dma-controller@40420000 {
211 compatible = "st,stm32mp25-dma3";
230 #dma-cells = <3>;
234 compatible = "st,stm32mp25-rifsc", "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 #access-controller-cells = <1>;
241 i2s2: audio-controller@400b0000 {
242 compatible = "st,stm32mp25-i2s";
244 #sound-dai-cells = <0>;
247 clock-names = "pclk", "i2sclk";
251 dma-names = "rx", "tx";
252 access-controllers = <&rifsc 23>;
257 #address-cells = <1>;
258 #size-cells = <0>;
259 compatible = "st,stm32mp25-spi";
266 dma-names = "rx", "tx";
267 access-controllers = <&rifsc 23>;
271 i2s3: audio-controller@400c0000 {
272 compatible = "st,stm32mp25-i2s";
274 #sound-dai-cells = <0>;
277 clock-names = "pclk", "i2sclk";
281 dma-names = "rx", "tx";
282 access-controllers = <&rifsc 24>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "st,stm32mp25-spi";
296 dma-names = "rx", "tx";
297 access-controllers = <&rifsc 24>;
301 spdifrx: audio-controller@400d0000 {
302 compatible = "st,stm32h7-spdifrx";
303 #sound-dai-cells = <0>;
306 clock-names = "kclk";
310 dma-names = "rx", "rx-ctrl";
311 access-controllers = <&rifsc 30>;
316 compatible = "st,stm32h7-uart";
322 dma-names = "rx", "tx";
323 access-controllers = <&rifsc 32>;
328 compatible = "st,stm32h7-uart";
334 dma-names = "rx", "tx";
335 access-controllers = <&rifsc 33>;
340 compatible = "st,stm32h7-uart";
346 dma-names = "rx", "tx";
347 access-controllers = <&rifsc 34>;
352 compatible = "st,stm32h7-uart";
358 dma-names = "rx", "tx";
359 access-controllers = <&rifsc 35>;
364 compatible = "st,stm32mp25-i2c";
366 interrupt-names = "event";
370 #address-cells = <1>;
371 #size-cells = <0>;
374 dma-names = "rx", "tx";
375 access-controllers = <&rifsc 41>;
380 compatible = "st,stm32mp25-i2c";
382 interrupt-names = "event";
386 #address-cells = <1>;
387 #size-cells = <0>;
390 dma-names = "rx", "tx";
391 access-controllers = <&rifsc 42>;
396 compatible = "st,stm32mp25-i2c";
398 interrupt-names = "event";
402 #address-cells = <1>;
403 #size-cells = <0>;
406 dma-names = "rx", "tx";
407 access-controllers = <&rifsc 43>;
412 compatible = "st,stm32mp25-i2c";
414 interrupt-names = "event";
418 #address-cells = <1>;
419 #size-cells = <0>;
422 dma-names = "rx", "tx";
423 access-controllers = <&rifsc 44>;
428 compatible = "st,stm32mp25-i2c";
430 interrupt-names = "event";
434 #address-cells = <1>;
435 #size-cells = <0>;
438 dma-names = "rx", "tx";
439 access-controllers = <&rifsc 45>;
444 compatible = "st,stm32mp25-i2c";
446 interrupt-names = "event";
450 #address-cells = <1>;
451 #size-cells = <0>;
454 dma-names = "rx", "tx";
455 access-controllers = <&rifsc 46>;
460 compatible = "st,stm32mp25-i2c";
462 interrupt-names = "event";
466 #address-cells = <1>;
467 #size-cells = <0>;
470 dma-names = "rx", "tx";
471 access-controllers = <&rifsc 47>;
476 compatible = "st,stm32h7-uart";
482 dma-names = "rx", "tx";
483 access-controllers = <&rifsc 36>;
487 i2s1: audio-controller@40230000 {
488 compatible = "st,stm32mp25-i2s";
490 #sound-dai-cells = <0>;
493 clock-names = "pclk", "i2sclk";
497 dma-names = "rx", "tx";
498 access-controllers = <&rifsc 22>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "st,stm32mp25-spi";
512 dma-names = "rx", "tx";
513 access-controllers = <&rifsc 22>;
518 #address-cells = <1>;
519 #size-cells = <0>;
520 compatible = "st,stm32mp25-spi";
527 dma-names = "rx", "tx";
528 access-controllers = <&rifsc 25>;
533 #address-cells = <1>;
534 #size-cells = <0>;
535 compatible = "st,stm32mp25-spi";
542 dma-names = "rx", "tx";
543 access-controllers = <&rifsc 26>;
548 compatible = "st,stm32mp25-sai";
551 #address-cells = <1>;
552 #size-cells = <1>;
554 clock-names = "pclk";
557 access-controllers = <&rifsc 49>;
560 sai1a: audio-controller@40290004 {
561 compatible = "st,stm32-sai-sub-a";
563 #sound-dai-cells = <0>;
565 clock-names = "sai_ck";
570 sai1b: audio-controller@40290024 {
571 compatible = "st,stm32-sai-sub-b";
573 #sound-dai-cells = <0>;
575 clock-names = "sai_ck";
582 compatible = "st,stm32mp25-sai";
585 #address-cells = <1>;
586 #size-cells = <1>;
588 clock-names = "pclk";
591 access-controllers = <&rifsc 50>;
594 sai2a: audio-controller@402a0004 {
595 compatible = "st,stm32-sai-sub-a";
597 #sound-dai-cells = <0>;
599 clock-names = "sai_ck";
604 sai2b: audio-controller@402a0024 {
605 compatible = "st,stm32-sai-sub-b";
607 #sound-dai-cells = <0>;
609 clock-names = "sai_ck";
616 compatible = "st,stm32mp25-sai";
619 #address-cells = <1>;
620 #size-cells = <1>;
622 clock-names = "pclk";
625 access-controllers = <&rifsc 51>;
628 sai3a: audio-controller@402b0004 {
629 compatible = "st,stm32-sai-sub-a";
631 #sound-dai-cells = <0>;
633 clock-names = "sai_ck";
638 sai3b: audio-controller@502b0024 {
639 compatible = "st,stm32-sai-sub-b";
641 #sound-dai-cells = <0>;
643 clock-names = "sai_ck";
650 compatible = "st,stm32h7-uart";
656 dma-names = "rx", "tx";
657 access-controllers = <&rifsc 39>;
662 compatible = "st,stm32h7-uart";
668 dma-names = "rx", "tx";
669 access-controllers = <&rifsc 31>;
674 compatible = "st,stm32mp25-sai";
677 #address-cells = <1>;
678 #size-cells = <1>;
680 clock-names = "pclk";
683 access-controllers = <&rifsc 52>;
686 sai4a: audio-controller@40340004 {
687 compatible = "st,stm32-sai-sub-a";
689 #sound-dai-cells = <0>;
691 clock-names = "sai_ck";
696 sai4b: audio-controller@40340024 {
697 compatible = "st,stm32-sai-sub-b";
699 #sound-dai-cells = <0>;
701 clock-names = "sai_ck";
708 #address-cells = <1>;
709 #size-cells = <0>;
710 compatible = "st,stm32mp25-spi";
717 dma-names = "rx", "tx";
718 access-controllers = <&rifsc 27>;
723 #address-cells = <1>;
724 #size-cells = <0>;
725 compatible = "st,stm32mp25-spi";
732 dma-names = "rx", "tx";
733 access-controllers = <&rifsc 28>;
738 compatible = "st,stm32h7-uart";
744 dma-names = "rx", "tx";
745 access-controllers = <&rifsc 37>;
750 compatible = "st,stm32h7-uart";
756 dma-names = "rx", "tx";
757 access-controllers = <&rifsc 38>;
762 compatible = "st,stm32mp25-rng";
765 clock-names = "core", "bus";
767 access-controllers = <&rifsc 92>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 compatible = "st,stm32mp25-spi";
781 dma-names = "rx", "tx";
782 access-controllers = <&rifsc 29>;
787 compatible = "st,stm32mp25-i2c";
789 interrupt-names = "event";
793 #address-cells = <1>;
794 #size-cells = <0>;
797 dma-names = "rx", "tx";
798 access-controllers = <&rifsc 48>;
803 compatible = "st,stm32mp25-csi";
809 clock-names = "pclk", "txesc", "csi2phy";
810 access-controllers = <&rifsc 86>;
815 compatible = "st,stm32mp25-dcmipp";
820 clock-names = "kclk", "mclk";
821 access-controllers = <&rifsc 87>;
826 compatible = "st,stm32mp25-combophy";
828 #phy-cells = <1>;
830 clock-names = "apb", "ker";
832 reset-names = "phy";
833 access-controllers = <&rifsc 67>;
834 power-domains = <&CLUSTER_PD>;
835 wakeup-source;
836 interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
841 compatible = "st,stm32mp25-sdmmc2", "arm,pl18x", "arm,primecell";
842 arm,primecell-periphid = <0x00353180>;
846 clock-names = "apb_pclk";
848 cap-sd-highspeed;
849 cap-mmc-highspeed;
850 max-frequency = <120000000>;
851 access-controllers = <&rifsc 76>;
856 compatible = "st,stm32mp25-dwmac", "snps,dwmac-5.20";
858 reg-names = "stmmaceth";
859 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
860 interrupt-names = "macirq";
861 clock-names = "stmmaceth",
862 "mac-clk-tx",
863 "mac-clk-rx",
866 "eth-ck";
873 snps,axi-config = <&stmmac_axi_config_1>;
874 snps,mixed-burst;
875 snps,mtl-rx-config = <&mtl_rx_setup_1>;
876 snps,mtl-tx-config = <&mtl_tx_setup_1>;
880 access-controllers = <&rifsc 60>;
883 mtl_rx_setup_1: rx-queues-config {
884 snps,rx-queues-to-use = <2>;
889 mtl_tx_setup_1: tx-queues-config {
890 snps,tx-queues-to-use = <4>;
897 stmmac_axi_config_1: stmmac-axi-config {
906 compatible = "st,stm32mp25-bsec";
908 #address-cells = <1>;
909 #size-cells = <1>;
921 rcc: clock-controller@44200000 {
922 compatible = "st,stm32mp25-rcc";
924 #clock-cells = <1>;
925 #reset-cells = <1>;
1006 access-controllers = <&rifsc 156>;
1009 exti1: interrupt-controller@44220000 {
1010 compatible = "st,stm32mp1-exti", "syscon";
1011 interrupt-controller;
1012 #interrupt-cells = <2>;
1014 interrupts-extended =
1103 compatible = "st,stm32mp25-syscfg", "syscon";
1108 #address-cells = <1>;
1109 #size-cells = <1>;
1110 compatible = "st,stm32mp257-pinctrl";
1112 interrupt-parent = <&exti1>;
1114 pins-are-numbered;
1117 gpio-controller;
1118 #gpio-cells = <2>;
1119 interrupt-controller;
1120 #interrupt-cells = <2>;
1123 st,bank-name = "GPIOA";
1128 gpio-controller;
1129 #gpio-cells = <2>;
1130 interrupt-controller;
1131 #interrupt-cells = <2>;
1134 st,bank-name = "GPIOB";
1139 gpio-controller;
1140 #gpio-cells = <2>;
1141 interrupt-controller;
1142 #interrupt-cells = <2>;
1145 st,bank-name = "GPIOC";
1150 gpio-controller;
1151 #gpio-cells = <2>;
1152 interrupt-controller;
1153 #interrupt-cells = <2>;
1156 st,bank-name = "GPIOD";
1161 gpio-controller;
1162 #gpio-cells = <2>;
1163 interrupt-controller;
1164 #interrupt-cells = <2>;
1167 st,bank-name = "GPIOE";
1172 gpio-controller;
1173 #gpio-cells = <2>;
1174 interrupt-controller;
1175 #interrupt-cells = <2>;
1178 st,bank-name = "GPIOF";
1183 gpio-controller;
1184 #gpio-cells = <2>;
1185 interrupt-controller;
1186 #interrupt-cells = <2>;
1189 st,bank-name = "GPIOG";
1194 gpio-controller;
1195 #gpio-cells = <2>;
1196 interrupt-controller;
1197 #interrupt-cells = <2>;
1200 st,bank-name = "GPIOH";
1205 gpio-controller;
1206 #gpio-cells = <2>;
1207 interrupt-controller;
1208 #interrupt-cells = <2>;
1211 st,bank-name = "GPIOI";
1216 gpio-controller;
1217 #gpio-cells = <2>;
1218 interrupt-controller;
1219 #interrupt-cells = <2>;
1222 st,bank-name = "GPIOJ";
1227 gpio-controller;
1228 #gpio-cells = <2>;
1229 interrupt-controller;
1230 #interrupt-cells = <2>;
1233 st,bank-name = "GPIOK";
1239 compatible = "st,stm32mp25-rtc";
1243 clock-names = "pclk", "rtc_ck";
1244 interrupts-extended = <&exti2 17 IRQ_TYPE_LEVEL_HIGH>;
1249 #address-cells = <1>;
1250 #size-cells = <1>;
1251 compatible = "st,stm32mp257-z-pinctrl";
1253 interrupt-parent = <&exti1>;
1255 pins-are-numbered;
1258 gpio-controller;
1259 #gpio-cells = <2>;
1260 interrupt-controller;
1261 #interrupt-cells = <2>;
1264 st,bank-name = "GPIOZ";
1265 st,bank-ioport = <11>;
1271 exti2: interrupt-controller@46230000 {
1272 compatible = "st,stm32mp1-exti", "syscon";
1273 interrupt-controller;
1274 #interrupt-cells = <2>;
1276 interrupts-extended =