Lines Matching +full:gated +full:- +full:fixed +full:- +full:clock
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
10 stdout-path = "serial2:1500000n8";
13 /* Unnamed gated oscillator: 100MHz,3.3V,3225 */
14 pcie30_port0_refclk: pcie30_port1_refclk: pcie-oscillator {
15 compatible = "gated-fixed-clock";
16 #clock-cells = <0>;
17 clock-frequency = <100000000>;
18 clock-output-names = "pcie30_refclk";
19 vdd-supply = <&vcc3v3_pi6c_05>;
22 vcc3v3_pcie2x1l0: regulator-vcc3v3-pcie2x1l0 {
23 compatible = "regulator-fixed";
24 regulator-name = "vcc3v3_pcie2x1l0";
25 regulator-min-microvolt = <3300000>;
26 regulator-max-microvolt = <3300000>;
27 startup-delay-us = <5000>;
28 vin-supply = <&vcc_3v3_s3>;
31 vcc3v3_bkey: regulator-vcc3v3-bkey {
32 compatible = "regulator-fixed";
33 enable-active-high;
35 pinctrl-names = "default";
36 pinctrl-0 = <&pcie_4g_pwen>;
37 regulator-name = "vcc3v3_bkey";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 startup-delay-us = <5000>;
41 vin-supply = <&vcc5v0_sys>;
44 vcc3v3_pcie30: vcc3v3_pi6c_05: regulator-vcc3v3-pi6c-05 {
45 compatible = "regulator-fixed";
46 enable-active-high;
48 pinctrl-names = "default";
49 pinctrl-0 = <&pcie30x4_pwren_h>;
50 regulator-name = "vcc3v3_pcie30";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 startup-delay-us = <5000>;
54 vin-supply = <&vcc5v0_sys>;
57 vcc5v0_host: regulator-vcc5v0-host {
58 compatible = "regulator-fixed";
59 enable-active-high;
61 pinctrl-names = "default";
62 pinctrl-0 = <&vcc5v0_host_en>;
63 regulator-name = "vcc5v0_host";
64 regulator-min-microvolt = <5000000>;
65 regulator-max-microvolt = <5000000>;
66 regulator-boot-on;
67 regulator-always-on;
68 vin-supply = <&vcc5v0_sys>;
90 interrupt-parent = <&gpio0>;
92 #clock-cells = <0>;
93 clock-output-names = "hym8563";
94 pinctrl-names = "default";
95 pinctrl-0 = <&hym8563_int>;
96 wakeup-source;
102 pinctrl-names = "default";
103 pinctrl-0 = <&pcie2_0_rst>;
104 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; /* PCIE20_1_PERST_L */
105 vpcie3v3-supply = <&vcc3v3_pcie2x1l0>;
110 data-lanes = <1 1 2 2>;
111 /* separate clock lines from the clock generator to phy and devices */
112 rockchip,rx-common-refclk-mode = <0 0 0 0>;
116 /* M-Key */
126 clock-names = "aclk_mst", "aclk_slv",
130 num-lanes = <2>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pcie30x2_perstn_m1_l>;
133 reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; /* PCIE30X2_PERSTn_M1_L */
134 vpcie3v3-supply = <&vcc3v3_pcie30>;
138 /* B-Key and E-Key */
148 clock-names = "aclk_mst", "aclk_slv",
152 pinctrl-names = "default";
153 pinctrl-0 = <&pcie30x4_perstn_m1_l>;
154 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; /* PCIE30X4_PERSTn_M1_L */
155 vpcie3v3-supply = <&vcc3v3_bkey>;
161 pcie2_0_rst: pcie2-0-rst {
167 pcie30x2_perstn_m1_l: pcie30x2-perstn-m1-l {
171 pcie_4g_pwen: pcie-4g-pwen {
175 pcie30x4_perstn_m1_l: pcie30x4-perstn-m1-l {
179 pcie30x4_pwren_h: pcie30x4-pwren-h {
185 hym8563_int: hym8563-int {
191 vcc5v0_host_en: vcc5v0-host-en {
199 pinctrl-0 = <&pwm2m1_pins>;
200 pinctrl-names = "default";
209 bus-width = <4>;
210 cap-mmc-highspeed;
211 cap-sd-highspeed;
212 disable-wp;
213 no-sdio;
214 no-mmc;
215 sd-uhs-sdr104;
216 vmmc-supply = <&vcc_3v3_s3>;
217 vqmmc-supply = <&vccio_sd_s0>;
222 pinctrl-0 = <&uart2m0_xfer>;
228 pinctrl-0 = <&uart6m0_xfer>;
229 pinctrl-names = "default";
235 pinctrl-0 = <&uart7m2_xfer>;
236 pinctrl-names = "default";
246 phy-supply = <&vcc5v0_sys>;
255 phy-supply = <&vcc5v0_host>;